Various Methods of DRAM Refresh

Category: DRAM
Manufacture: Micron Semiconductor Products, Inc.
Datasheet: Download this application note

This article was originally published in 1994.
on before repeating the task. When not being refreshed, the DRAM can be read from or written to.
DRAM refresh is the topic most misunderstood by designers due to the many ways refresh can be accomplished. This article addresses the most often asked questions about refresh. The two basic means of performing refresh, distributed and burst, are explained first, followed by the various ways to accomplish refresh: RAS#-ONLY REFRESH, CAS#-BEFORE-RAS# REFRESH and HIDDEN REFRESH.
Refresh may be achieved in a burst method by performing a series of refresh cycles, one right after the other until all rows have been accessed. During refresh other commands are not allowed. Below is a drawing representing burst and distributed refresh. For example: a 4 Meg x 1 requires 1,024 consecutive refresh cycles, each of which will use 130ns (tRC) for a 70ns device: 1,024 cycles 130ns = 133,120ns = 0.133ms 16ms - 0.133ms = 15.867ms Approximately 0.13ms would be spent performing refresh, and the remaining 15.87ms could be spent reading and writing; then burst refresh would occur again, and so on. Distributed refresh is the more common of the two refresh categories. The DRAM controller is set up to perform a refresh cycle every 15.6s. Usually, this means the controller allows the current cycle to be completed and then holds off all instructions while a refresh is performed on the DRAM. The requested cycle is then allowed to resume.
DRAMs are often referred to as either "standard refresh" or "extended refresh." Dividing the specified refresh time by the number of cycles required will determine if the DRAM is a standard refresh or an extended refresh device. If the result is 15.6s, it is a standard refresh device, while a result of 125s indicates an extended refresh device. Table 1 lists some of the standard DRAMs and their refresh specifications.
Table 1 Standard DRAMs and Refresh Specifications
DRAM 4 Meg x 1 256K x 16 256K x 16 (L version) 4 Meg x 4 (2K) 4 Meg x 4 (4K) REFRESH TIME 16ms 8ms 64ms 32ms 64ms NUMBER OF CYCLES 1,024 512 512 2,046 4,096 REFRESH RATE 15.6s 15.6s 125s 15.6s 15.6s
There are different cycles you can use to refresh DRAMs, all of which can be used in a distributed or burst method. There are three types listed in a standard data sheet: RAS#-ONLY REFRESH CAS#-BEFORE-RAS# REFRESH HIDDEN REFRESH
Distributed Refresh Burst Refresh
Distributing the refresh cycles so that they are evenly spaced is known as distributed refresh. To perform distributed refresh on a standard DRAM, execute a refresh cycle every 15.6s such that all rows are turned
Each pulse represents a refresh cycle
Required time to complete refresh of all rows
Figure 1 Burst and Destributed Refresh 1
Micron Technology, Inc., reserves the right to change products or specifications without notice. 1999, Micron Technology, Inc.
TN-04-30 DT30.p65 Rev. 2/99
To perform a RAS#-ONLY REFRESH, a row address is put on the address lines and then RAS# is dropped. When RAS# falls, that row will be refreshed and as long as CAS# is held HIGH, the DQs will remain open. (See Figure 2.) It is the DRAM controller's function to provide the addresses to be refreshed and make sure that all rows are being refreshed in the appropriate amount of time. The row order of refreshing does not matter; what is important is that each row be refreshed in the specified amount of time. counter. The user does not have to supply or keep track of row addresses. A drawing of one CBR REFRESH cycle is shown in Figure 3. CAS# must be held LOW before and after RAS# falls to meet tCSR and tCHR. Figure 4 shows three CBR REFRESH cycles. In this drawing, CAS# stays LOW and only RAS# toggles. Every time RAS# falls a refresh cycle is performed. CAS# may be toggled each time, but it's not necessary.
Since CBR REFRESH uses the internal counter and not an external address, the address buffers are powered-down. For power-sensitive applications, this can be a benefit because there is no additional current used in switching address lines on a bus, nor will the DRAMs pull extra power if the address voltage is at an intermediate state.
CAS#-BEFORE-RAS# REFRESH, also known as CBR REFRESH, is a frequently used method of refresh because it is easy to use and offers the advantage of a power savings. A CBR REFRESH cycle is performed by dropping CAS# and then dropping RAS#. One refresh cycle will be performed each time RAS# falls. WE# must be held HIGH while RAS# falls. The DQs will remain open during the cycle. Here's how CBR REFRESH works. The die contains an internal counter which is initialized to a random count when the device is powered up. Each time a CBR REFRESH is performed, the device refreshes a row based on the counter, and then the counter is incremented. When CBR REFRESH is performed again, the next row is refreshed and the counter is incremented. The counter will automatically wrap and continue when it reaches the end of its count. There is no way to reset the
Since CBR REFRESH uses its own internal counter, there is not a concern about the controller having to supply the refresh addresses. Virtually all DRAMs support CBR REFRESH and the 15.6s refresh rate, so you can design for CBR REFRESH at the distributed rate of 15.6s and plug in many different DRAMs without having to worry about refresh. For example, the 4 Meg x 4 comes in two versions: 2,048 cycles in 32ms 4,096 cycles in 64ms
One refresh cycle when RAS# falls
Figure 2 RAS#-Only Refresh
TN-04-30 DT30.p65 Rev. 2/99
Micron Technology, Inc., reserves the right to change products or specifications without notice. 1999, Micron Technology, Inc.

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