Application notes section: Clocks and Timers

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Category: Application notes => Section: Clocks and Timers

Titles from 1 to 200 on total number of: 433

-Crystal Design Notes
-Quartz Crystal Theory of Operation
12-Bit Thermometer Using an 8-Bit C and Assembler
12-Bit Thermometer Using an 8-Bit C and Assembler
1522 Frequently Asked Questions
1522 GenLock Typical Performance
1522 Line-Locked Application Design Supplement
1522 Line-Locked Application Design Supplement
1523 Application Guide
1523 Demo Board Schematics
1523 Designing a Custom PECL Interface
1523 ICS1523 FAQ
1523 Image Stability
1523 Latch Problems
1562B Demo Board Schematics
1562B Download Application Note
3.0 Volt TTL
3.3V LVPECL Driver Termination 843003
3.3V LVPECL Driver Termination App Notes 843003-01i
3.3V LVPECL Driver Termination App Notes 843256
3.3V LVPECL Driver Termination App Notes 84327
342 VersaClock App Note
343 VersaClock App Note
345 VersaClock App Note
348 VersaClock App Note
4-Gbit Fibre Channel Frequency Control Design
507-01 Demo Board Instructions
525-01 Demo board
527-03 / -04 Demo Board Instructions
601-21 Demo Board Instructions
84327 Datasheet
A comparison of 125MHz CMOS oscillators Crystal versus SAW technology
A Comparison of the NBC12429 and MC12429 Programmable PLL Clock Synthesizers
A General Guideline: How to Use the CDCF5801A for Phase Alignment/Adjustment (Rev. B)
A Programmatic Approach to Calculating DS1085 Programmable-Oscillator Register Values
A Programmatic Approach to Calculating DS1085 Programmable-Oscillator Register Values
AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C)
Accessing the DS1318 Clock Registers
Accessing the DS1318 Clock Registers
ADIsimCLK Reference Design Files
Advantage of Using TI's Lowest Jitter Differential Clock Buffer
AMIS Timing Generator
AN-150 Clock and Signal Distribution
AN-154: Estimating Power Dissipation in CMOS
AN-155 PLL Clock Generators
AN-226: Programming Turboclocks
AN-227: Using PLL Clock Drivers
AN-228: Programming Turboclock II
AN-229: Zero Delay Buffers
AN-234: Programmable Clock Application Note
AN-236: 49FCT3805D Jitter Performance
AN-237: PLL Lock Indicator
AN-238: 5T982x / 5T989x FAQ
AN-239: 5V9885 FAQ
AN-240: 5V9885 Applications and Software
AN-43: High-Speed Clocking Device Power Supply
AN-45: TurboClock Test Mode and Special Features
AN-46: FAQ About QSI 5919 and Turboclocks
AN-657: ADN2812 Evaluation Board
AN-82 Clock Distribution with Guaranteed Skew
Antenna Impedance Matching Considerations
Appendix A - Application Notes
Appendix B - Test Circuits and Waveforms
Appendix C - Environmental and Mechanical Specs
Appendix D - Value Added Options
Appendix E - Recomemmended Solder Reflow
Appendix F - Recommended Handling
Appendix G - Standard Markings
Application and Design Considerations for CDC5xx Phase-Lock Loop Clock Drivers
Application Examples for CDCUx877x PLL family
Application Examples for CDCUx877x PLL family
Approved VCXO Crystals
Automated Production Testing for the V/S/R types and TRU050 Products
²C Multiple Read
Band Switching Z-Comm VCOs
Benefits of the DS32X35 Accurate Real-Time Clock with Ferroelectric Random Access Memory (RTC + FRAM...
Benefits of the DS32X35 Accurate Real-Time Clock with Ferroelectric Random Access Memory (RTC + FRAM...
Benefits of Using TI's Non-PLL Clock Buffer Best in Class Phase Noise/Phase
Board Mounting Considerations for FCBGA Packages
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)
Buffered Linear-Ramp Generator Operates Rail-to-Rail from a Single Supply
Buffered Linear-Ramp Generator Operates Rail-to-Rail from a Single Supply
Building a Low-Cost White-Noise Generator
Building a Low-Cost White-Noise Generator
Calculating ML Cell Life for an RTC Backup Operation
Calculating ML Cell Life for an RTC Backup Operation
Calibrating the DS1340 Real-Time Clock
Calibrating the DS1340 Real-Time Clock
Case Study: When Reliability is Critical
CD-700 A Quartz Stabilized PLL
CD-700/TRU-050 Code Mark Inversion (CMI) Input Databy Jan Yang and Dave Lane
CDCL6010 as a Frequency Synthesizer and Jitter Cleaner
CDCL6010 as a Frequency Synthesizer and Jitter Cleaner
CDCM1802/CDCM1804
CDCU877 PLL vs JEDEC DDR2 PLL Specification (Rev. A)
CDCU877 PLL vs JEDEC DDR2 PLL Specification (Rev. A)
Ceramic Resonator
Clock and Data Recovery Circuit Operation and Set-up
Clock and Data Recovery Setup
Clock Distribution in High-Performance PCs (Rev. A)
Clock Management Design Using Low Skew and Low Jitter Devices
Comparing VectronCrystal-Based PECL Oscillator with a SAW-Based Equivalent
Complementary Output ECL (PECL)
Configuring and Applying the MC74HC4046A Phase-Locked Loop
Crystal Glossary
Crystal Oscillator Has Dual or Differential Outputs
Crystal Oscillator Has Dual or Differential Outputs
Crystal Timing Budget and Accuracy for FemtoClocks
Data Slicing Modes
DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML
Decoupling Requirements for the DS1077/DS1085 EconOscillators
Decoupling Requirements for the DS1077/DS1085 EconOscillators
Defining Skew, Propagation-Delay, Phase Offset (Phase Error)
Defining Skew, Propagation-Delay, Phase Offset (Phase Error)
Definition of Absolute Pull Range
Demonstration Kit (EVK-53050) Hardware
Describes proper crystal Cload selection
Design and Layout Guidelines for the CDCVF2505 Clock Driver
Design Considerations for All-Silicon Delay Lines
Design Considerations for All-Silicon Delay Lines
Design Considerations for Dallas Semiconductor Real-Time Clocks
Design Considerations for Dallas Semiconductor Real-Time Clocks
Design Considerations for TI's CDCV857/CDCV857A DRR PLL
Design Considerations for TI's CDCV857/CDCV857A DRR PLL
Design Considerations for TI's CDCV857/CDCV857A/CDCV855 DRR PLL (Rev. A)
Design Considerations for TI's CDCV857/CDCV857A/CDCV855 DRR PLL (Rev. A)
Designing with PECL (ECL at +5.0 V)
Device Characteristics of the DS1045 Dual 4-Bit Programmable Delay Line
Device Characteristics of the DS1045 Dual 4-Bit Programmable Delay Line
DS1020/DS1021 8-Bit Programmable Delay Lines
DS1020/DS1021 8-Bit Programmable Delay Lines
DS1077 5V EconOscillator Architecture and Online Interactive Frequency Calculator
DS1077 5V EconOscillator Architecture and Online Interactive Frequency Calculator
DS1077L EconOscillator Architecture and Online Interactive Frequency Calculator
DS1077L EconOscillator Architecture and Online Interactive Frequency Calculator
DS1086 Frequency Calculator and Frequency Calculation Algorithm
DS1086 Frequency Calculator and Frequency Calculation Algorithm
DS1375 Power Line to 60Hz Clock
DS1375 Power Line to 60Hz Clock
DS1670 Portable System Controller
DS1670 Portable System Controller
DS1685/87 and DS17X85/87 Accessing Extended User RAM
DS1685/87 and DS17X85/87 Accessing Extended User RAM
Dual Purposes: Data Buffer, The Other Face of CDCP1803
Dual Purposes: Data Buffer, The Other Face of CDCP1803
ECL Clock Distribution Techniques
ECLinPS Plus Spice Modeling Kit
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide
EconOscillator Comparison
EconOscillator Comparison
EMI Prevention in Clock-Distribution Circuits
Estimating Super Capacitor Backup Time on Trickle-Charger Real-Time Clocks
Estimating Super Capacitor Backup Time on Trickle-Charger Real-Time Clocks
Evacuated Miniature Crystal Oscillators (EMXOTM)
Evaluating the Accuracy of Maxim Real-Time Clocks (RTCs)
Evaluating the Accuracy of Maxim Real-Time Clocks (RTCs)
EX-380/385 Series (EMXOTM) Application Note
Extending to Frequencies Outside of the 403MHz Target
Extending to Frequencies Outside the 403MHz Target
Extremely accurate timekeeping over temperature using adaptive calibration
Family Characteristics for MECL 10H and MECL 10K
FAQ About the Integrated-Crystal Package Option
FAQ About the Integrated-Crystal Package Option
Ferrite Bead Recommendations
First Time Users
First Time Users
Frequency Calculator for the DS1085/DS1085L EconOscillator
Frequency Calculator for the DS1085/DS1085L EconOscillator
Frequency Calculator for the DS1086L
Frequency Calculator for the DS1086L
Frequency Calculator for the DS1090
Frequency Calculator for the DS1090
Frequency Calculator for the DS1094L
Frequency Calculator for the DS1094L
General Guidelines: CDC7005 as a Clock Synthesizer and Jitter Cleaner
General Guidelines: CDC7005 as a Clock Synthesizer and Jitter Cleaner (Rev. A)
Generating Early Clock using TI's CDCVF2509/CDCVF2510 PLLs
Generating Early Clock using TI's CDCVF2509/CDCVF2510 PLLs
High Q, precision SC cut resonators with low acceleration sensitivity Technical paperby P. Morley, R...
High Speed Clock Distribution Design Techniques for CDC 509/516/2509/2510/2516 (Rev. A)
High Speed Layout Guidelines
High Speed Layout Guidelines
High-frequency silicon oscillator devices 10 - 12 - 16 MHz family
High-Speed Pulse Generator Has Programmable Levels
High-Speed Pulse Generator Has Programmable Levels
How Delay Lines Work
How Delay Lines Work
How to 'Center' a Down-Dithering EconOscillator
How to 'Center' a Down-Dithering EconOscillator
How to use M41ST87 tamper detect and RAM clear
How to Use the DS1678 Real-Time Event Recorder
How to Use the DS1678 Real-Time Event Recorder
HSTL Clock Buffer Using the CDCV850
HSTL Clock Buffer Using the CDCV850
ICS1526 Schematics
ICS307-03 Demo Board Instructions
ICS500 Family demo board instructions
ICS525 Demo board
ICS527-01/-02 Demo Board Instructions
Implementing a CDC7005 Low Jitter Clock Solution for HIgh Speed High IF ADC Dev

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