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Application notes section: Interface and Interconnect
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Category:
Application notes
=> Section:
Interface and Interconnect
Titles from 1 to 200 on total number of: 942
(AN-1) Understanding the Single-Ended SCSI Bus
(AN-2) Ultra2 SCSI White Paper
100336 Four-Stage Counter/Shift Register
12-mm Tape-and-Reel Component-Delivery System
42000 High Speed CAN Transceiver Topology Aspects of a High Speed CAN Bus
5-V To 3.3-V Translation With the SN74CBTD3384 (Rev. B)
54BGA Package
74C Family Characteristics
A Look at Boundary Scan From a Designer's Perspective
ABT APPLICATIONS: Avoiding BUS Contention
ABT Ratings, Specifications and Waveforms
AC Characteristics of MM74HC High Speed CMOS
Add USB to Anything
Add USB to Anything
Advanced Bus-Matching/Byte-Swapping For Internetworking FIFO Applications (Rev. A)
An Introduction to Fairchild Switch Products
An Optimized DCE Interface for V.34 Modems Using the DS8933 and DS8934 Line Drivers and Receivers
AN-027, Compensating for Zero Order Hold Effects
AN-030, CMOS Current Output D/A Converter Design Concepts for Wide Bandwidth Applications
AN-1450/AN-1550, ST16C1450 and ST16C1550 Application Example
AN-2450/AN-2550 - ST16C2450 and ST16C2550 Application Example
AN-450/AN-550, ST16C450/550 Application Example
AN-452, ST16C452 Application Example
AN-454, ST16C454 Application Example
AN-5053 Using Fairchild uSerDes Devices with a Synchronous Pixel Interface
AN-508, Hot-Plug Implementation in the PES24N3 PCIe Switch
AN-509, Hot-Plug Implementation in the PES12N3 PCIe Switch
AN-531, PCIe System Interconnect Software Architecture
AN-532, PES24N3/PES24NT3 PCIe Switch Performance with External Cabling
AN-533, PES12N3/PES12NT3 PCIe Switch Performance with External Cabling
AN-571, PCIe System Interconnect SW Architecture for x86-based Systems
AN-6015 FSHDMI04 Applications Guide
AN-6019 Fairchild Analog Switch Products ESD Test Methodology Overview
AN-6019C Fairchild Analog Switch Products ESD Test Methodology Overview - Simplified Chinese
AN-6022 Using the FSUSB30 to Comply with USB 2.0 Fault Condition Requirements
AN-6031 Using SPI Read and Write with the uSerDes FIN324C
AN-6036SC FSHDMI04
AN-6036TC FSHDMI04
AN-6047 FIN324C Reset and Standby
AN-6047K FIN324C Reset and Standby Korean Translation
AN-6059SC Application Guide for FSHDMI08 Target Applications and Switch Overview (Simplified Chinese...
AN-6064 FSHDMI311 FCB Layout Guidelines DVI / HDMI Repeater
AN-6064SC FSHDMI311 PCB Layout Guidelines DVI/HDMI Repeater (Simplified Chinese)
AN-637: ADN2848 AC-Coupled Optical Evaluation Kit
AN-643 Closed-LoopControl Circuit Implementation of the ADuC832 MicroConverterIC and theAD8305 Logar...
AN-650, ST16C650 Application Example
AN-658: Optical Channel Identification on the ADN284x Laser Drivers (Part I)
AN-670: 0: A Complete EDFA/Raman Pump and CW Laser Solution
AN-705: 05: ADN8830-EVAL TEC Controller Instructions
AN-745: Implementing the Auto-Offset Function on the AD9985
AN-746: Supporting FDDI with the ADN2812
AN-762: ADN2891 Evaluation Board
AN-775: Implementing the Auto-Offset Function on the AD9880
AN-840 Companion Code
Analog Switch Expands I2C Interface
Analog Switch Expands I2C Interface
ANI-01, 1.8V RS232 Interface Using SP3203E & SP6661
ANI-04, SP503 Application Note
ANI-05, SP504 Application Note
ANI-07, Designing with the SP505, SP506, & SP507 Multi-Protocol Serial Transceivers
ANI-08, SP508 Multiprotocol Transceiver
ANI-09, Connecting SP5301 to MPC850 PowerQUICC
ANI-10, Charge Pump Capacitor Selection Guidefor 3V RS-232 Products
ANI-11, RS-232 Isolated Interface
ANI-12, RS-485 Isolated Interface
ANI-13, RS-485 and RS-422 Physical Topologies
ANI-14, DTE and DCE Terminology Explained
ANI-15, Upgrade from the 3241 to SP3243E
ANI-16, Design Guide for Multi-Protocol Serial Ports
ANI-17, Multiprotocol DTE and DCE Options
ANI-19, Selecting Charge Pump Capacitors for Serial RS-232 Transceivers
ANI-20, Advanced Features of the SP3070E-SP3078E and SP3080E- SP3088E High Performance RS-485 Transc...
ANI-21, SP3070E-SP3078E Guidelines for Failsafe Biasing when Applied in Multi-Voltage Networks
ANP-01, Using Sipex PWM Controllers for BoostConversion
ANP-03, Thermal Calculator
ANP-04, CAD Layout Recommendations for thePowerBlox Family
ANP-05, Thermal Resistance on SP765x Devices
ANP-06, PowerBloxTM in Distributed Power Architectures
ANP-07, Using SP6134 to Provide a High Output Boost to Drive
ANP-09, Using SP6652 For a Positive to Negative Buck Boost Converter
ANP-12, Low Cost, High Performance DDR Termination Using SP2996B
ANP-13, Applying the SP6121 as a Synchronous Buck-Boost 1.5A K2 LUXEON Driver
ANP-14, Understanding and Selecting a Multi-Voltage Supervisor Featuring the SP6330 Family
ANP-15, Voltage Mode Control The Modulator inContinuous Current Mode (CCM) of operation
ANP-16, Loop Compensation of Voltage-Mode Buck Converters
ANP-16, Type III Loop Compensation Calculator
ANP-18, Selecting Appropriate Compensation: Type-II or Type-III
ANP-18, Type II Loop Compensation Calculator
ANP-19, SP7611A/12A/14A LED Current Setting
ANP-21, Low Cost Backlight Solution Using Sipex Low-Side Driver
ANP-24, SP6656 for Dynamically Adjusting Output Voltage
ANP-25, PowerBlox Thermal Analysis
ANP-27, An Alternative to POLA Modules PowerBlox
Application Brief: FSA3357 Single Pole/Triple Throw Eliminates Second Single Pole/Double Throw and R...
Application Brief: FSAL200 LAN Switch Reduces Component Cost for Laptop PCs Using Docking Stations
Application Brief: Multiple Display Load Isolation Using the FSAV330
Application Guide for FSHDMI08 Target Applications and Switch Overview
Application Note 1031 TIA/EIA-422-B Overview
Application Note 1040 LVDS Performance Bit Error Rate (BER) Testing Test Report 2
Application Note 1057 Ten Ways to Bulletproof RS-485 Interfaces
Application Note 1088 LVDS Signal Quality Cable Drive Measurements using Eye Patterns Test Report 3
Application Note 1110 LVDS Quad Dynamic I CC vs Frequency
Application Note 1115 DS92LV010A Bus LVDS Transceiver Ushers in a New Era of High-Performance Backpl...
Application Note 1173 High Speed BUS LVDS Clock DistributionUsing the DS92CK16 Clock Distribution De...
Application Note 1194 Failsafe Biasing of LVDS Interfaces
Application Note 1217 How to Validate BLVDS SER/DES Signal Integrity Using an Eye Mask
Application Note 1238 Wide Bus Applications Using Parallel BLVDS SerDes Devices
Application Note 1259 SCANSTA112 Designers Reference
Application Note 1263 DP83865 Gig PHYTER V 10/100/1000 Ethernet Physical Layer Design Guide
Application Note 1301 Dual Foot Print Layout Notes for DP83865 Gig PHYTER V and DP83847 DS PHYTER II
Application Note 1312 Scan Bridge (STA111/STA112) Timing
Application Note 1313 SCAN90CP02 Design for Test Features
Application Note 1313 SCAN90CP02 Design for Test Features
Application Note 1329 DP83865 and DP83864 Gigabit Physical Layer Device Trouble Shooting Guide
Application Note 1334 The LMH0030 in Segmented Frames Applications
Application Note 1336 LMH0030 or LMH0031 Control Port Bussed Operation
Application Note 1340 Simplified Programming of Xilinx Devices Using a SCANSTA111/112 JTAG Chain Mux
Application Note 1340 Simplified Programming of Xilinx Devices Using a SCANSTA111/112 JTAG Chain Mux
Application Note 1347 PCB Layout Techniques for Adaptive Cable Equalizers
Application Note 1372 LMH0034 PCB Layout Techniques
Application Note 1376 External Serial Interface Reduces Simultaneous Switching Output Noise in FPGAs
Application Note 1376 External Serial Interface Reduces Simultaneous Switching Output Noise in FPGAs
Application Note 1389 Setting Pre-Emphasis Level for DS40MB200 Dual 4Gb/s Mux/Buffer
Application Note 1398 Printed Circuit Board Design Techniques for DS40MB200
Application Note 1399 Enabling Redundancy in Multi-Gigabit Links with DS40MB200 Mux/Buffer
Application Note 1401 DP83848 - Single 10/100 Mb/s Ethernet Transceiver Energy Detect Mode
Application Note 1405 DP83848 Single 10/100 Mb/s Ethernet Transceiver Reduced Media Independent Inte...
Application Note 1408 Designing Power Over Ethernet Using LM5070 and DP83865
Application Note 1425 Differences Between National Semiconductor 10/100 Mb/s Ethernet Physical Layer...
Application Note 1469 PHYTER Design Layout Guide
Application Note 1470 DP83847 to DP83848C/I/YB PHYTER System Rollover Document
Application Note 1475 DP83847 to DP83848M/T/H PHYTER Mini System Rollover Document
Application Note 1499 DP83846 to DP83848C/I/YB PHYTER System Rollover Document
Application Note 1503 Designing an ATCA Compliant M-LVDS Clock Distribution Network
Application Note 1506 DP83843 to DP83848C/I/YB PHYTER System Rollover Document
Application Note 1507 DP83848 and DP83849 100Mb Data Latency
Application Note 1508 DP83849 Cable Diagnostics
Application Note 1509 PhyterDual Flexible Port Switching
Application Note 1511 Cable Discharge Event
Application Note 1519 DP83848 PHYTER Transformerless Ethernet Operation
Application Note 1538 Interfacing Nationals DS90CR218A and LM98714
Application Note 1540 Power Measurement of Ethernet Physical Layer Products
Application Note 1548 PHYTER 100 Base-TX Reference Clock Jitter Tolerance
Application Note 1558 Clocking High-Speed A/D Converters
Application Note 1564 LXT971/972A to DP83848C/I/YB PHYTER System Rollover Document
Application Note 1565 LXT972M to DP83848C/I/YB PHYTER System Rollover Document
Application Note 1565 LXT972M to DP83848C/I/YB PHYTER System Rollover Document
Application Note 1613 Extending the Reach of HDMI, DVI and CAT5 Cables Using the DS16EV5110 Cable Eq...
Application Note 1728 IEEE 1588 Precision Time Protocol Time Synchronization Performance
Application Note 1729 DP83640 IEEE 1588 PTP Synchronized Clock Output
Application Note 1730 DP83640 Synchronous Ethernet Mode: Achieving Sub-nanosecond Accuracy in PTP Ap...
Application Note 1734 Using the LMK03000C to Clean Recovered Clocks
Application Note 1794 Using RMII Master Mode
Application Note 1821 CPRI Repeater System
Application Note 1821 CPRI Repeater System
Application Note 1826 Extending the Reach of a FPD-Link II Interface with Cable Drivers and Equalize...
Application Note 1838 IEEE 1588 Boundary Clock and Transparent Clock Implementation Using the DP8364...
Application Note 1862 Reducing Radiated Emissions in Ethernet 10/100 LAN Applications
Application Note 1864 Phase Synchronization with Multiple Devices and Frequencies
Application Note 1865 Frequency Synthesis and Planning for PLL Architectures
Application Note 1865 Frequency Synthesis and Planning for PLL Architectures
Application Note 214 Transmission Line Drivers and Receivers for TIA/EIA Standards RS-422 and RS-423
Application Note 409 Transceivers and Repeaters Meeting the EIA RS-485 Interface Standard
Application Note 438 Low Power RS-232C Driver and Receiver in CMOS
Application Note 454 Automotive Multiplex Wiring
Application Note 457 High Speed, Low Skew RS-422 Drivers and Receivers Solve Critical System Timing...
Application Note 805 Calculating Power Dissipation for Differential Line Drivers
Application Note 847 FAILSAFE Biasing of Differential Buses
Application Note 876 Inter-Operation of the DS14C335 with +5V UARTs
Application Note 903 A Comparison of Differential Termination Techniques
Application Note 904 An Introduction to the Differential SCSI Interface
Application Note 914 Understanding Power Requirements in RS-232 Applications
Application Note 915 Automotive Physical Layer SAE J1708 and the DS36277
Application Note 915 Automotive Physical Layer SAE J1708 and the DS36277
Application Note 967 LocalTalk Physical Layer Alternatives
Application Note 967 LocalTalk Physical Layer Alternatives
Application Note 971 An Overview of LVDS Technology
Application Note 971 An Overview of LVDS Technology
Application Note 977 LVDS Signal Quality Jitter Measurements Using Eye Patterns Test Report 1
Application Note: MIL-STD-1553 Remote Terminal Using SRAM for Host Interface
Application of the SN74SSTV32852 in Stacked, Low-Profile (1U) PC-1600/2100 DIMMs
Application of the SN74SSTVF16857 in Planar PC2700 (DDR-333) RDIMMs
Applications Using the GTLP10B320
Backplane Designer's Guide - Section 1 - Introduction
Backplane Designer's Guide - Section 2 - Backplane Protocols
Backplane Designer's Guide - Section 3 - Backplane Architecture
Backplane Designer's Guide - Section 4 - Backplane Design Considerations
Backplane Designer's Guide - Section 5 - Backplane Signal Conditioning
Backplane Designer's Guide - Section 6 - Noise, Cross-talk, Jitter, Skew, and EMI
Backplane Designer's Guide - Section 7 - Backplane Transceiver Technologies
Backplane Designer's Guide - Section 8 - Mechanical Considerations
Backplane Designer's Guide - Section 9 - Layout Considerations
Bergeron Method: Graphically Determine Line Reflections In Transient Phenomena
BGA Schematic
BGA Tape and Reel Specifications
Board-Mount Evaluation of Tin-Plated Component Leads
Boundary Scan Speeds Static Memory Tests
Boundary-Scan, an Enabling Technology for System Level Embedded Test
Bringing Up a MAX3420E System
Bringing Up a MAX3420E System
Titles from 1 to 200 on 942
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