|Category||Interface and Interconnect => DVI (Digital Visual Interface)|
|Description||DVI, HDMI Retimer With Input Equalization And Output De-Emphasis
The DS34RT5110 is a 10.2 Gbps (3 x 3.4 Gbps) high performance re-clocking device that supports 3 Transition Minimized Differential Signaling (TMDS®) data channels and a single clock channel over DVI™ v1.0, and HDMI™ v1.3a data rates up to 3.4 Gbps for each data channel. The device incorporates a configurable receive equalizer, a clock and data recovery (CDR) circuit and a de-emphasis driver on each data channel. The clock channel feeds a high-performance phase-locked loop (PLL) that regenerates a low jitter output clock for data recovery.
|Company||National Semiconductor Corporation|
|Datasheet||Download DS34RT5110 datasheet
|DS34RT5110 DVI, HDMI Retimer with Input Equalization and Output De-Emphasis
DVI, HDMI Retimer with Input Equalization and Output DeEmphasis
The a 10.2 Gbps x 3.4 Gbps) high performance re-clocking device that supports 3 Transition Minimized Differential Signaling (TMDS®) data channels and a single clock channel over DVITM v1.0, and HDMITM v1.3a data rates to 3.4 Gbps for each data channel. The device incorporates a configurable receive equalizer, a clock and data recovery (CDR) circuit and a de-emphasis driver on each data channel. The clock channel feeds a high-performance phaselocked loop (PLL) that regenerates a low jitter output clock for data recovery. The DS34RT5110 equalizes and retimes greater than 25 meters 28 AWG of HDMI cable for 1080p resolution with 12 bit deep color depth (2.25 Gbps), to a low jitter version of the clock and data signal outputs, reducing both deterministic and random jitter. Several devices can be cascaded for long links without degrading signal fidelity. Obtaining total jitter UI or less over the supported data rates. This low level of output jitter provides system designers with extra margin and flexibility when working with stringent timing budgets. The transmitter supports configurable transmit de-emphasis so the output can be optimized for driving additional lengths of cables or FR4 traces.Features
Optimized for HDMI/DVI repeater applications TMDS compatible inputs with configurable receive
equalization supporting data rates to 3.4 Gbps emphasis
TMDS compatible outputs with configurable transmit de Dedicated CDR on each data channel reduces jitter
transfer, enabling multiple devices to be cascaded without impairing signal fidelity Capable of multi-hop extension of HDMI/DVI applications at data rates between 250 Mbps and 3.4 Gbps Resistor adjustable differential output voltage for AC coupled Cat5e and Cat6 extension applications 2 equalizer settings for a wide range of cable reaches at different data rates Total Output Jitter at 2.25 Gbps Total Output Jitter at 3.4 Gbps DVI 1.0 and HDMI v1.3a compatible TMDS source and sink interface mm 48 pin LLP package >8 kV HBM ESD protection +70 °C operating temperatureApplications
Digital Routers HDMI / DVI Extender Multi-hops Source Applications Video Cards Blu-ray DVD Players Game Consoles Sink Applications High Definition Displays Projectors
Pin Name C_IN- C_IN+ D_IN2- D_IN2+ C_OUTC_OUT+ DE1 DE0 Device Control BYPASS 47 I, LVCMOS Reclocker enable control. Internally pulled low as default. H = Reclock and De-Emphasis function is bypassed. L = Normal operation. Pin Number I/O, Type I, CML I, CML I, CML I, CML O, CML O, CML O, CML O, CML Description Inverting and non-inverting TMDS Clock inputs to the equalizer. An on-chip 50 terminating resistor connects C_IN+ to VDD and C_IN- to VDD. Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50 terminating resistor connects D_IN0+ to VDD and D_IN0- to VDD. Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50 terminating resistor connects D_IN1+ to VDD and D_IN1- to VDD. Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50 terminating resistor connects D_IN2+ to VDD and D_IN2- to VDD. Inverting and non-inverting TMDS outputs from the equalizer. Open collector. Inverting and non-inverting TMDS outputs from the equalizer. Open collector. Inverting and non-inverting TMDS outputs from the equalizer. Open collector. Inverting and non-inverting TMDS outputs from the equalizer. Open collector. High Speed Differential I/O
Equalization Control I, LVCMOS EQ2, EQ1 and EQ0 select the equalizer boost level for EQ channels. Internally pulled LOW as default. See Table 1.
De-Emphasis Control I, LVCMOS DE1, DE0 select the DE-emphasis level for output drivers. Internally pulled low as default. Refer to Table 2.
I, LVCMOS Enable Output Drivers. Internally pulled HIGH as default. H = normal operation (enabled). L = standby mode. I, LVCMOS Clock channel mode control. Internally pulled LOW as default. H = Clock channel is bypassed. L = Normal operation. O, LVCMOS Signal Detect Output pin. H = signal detected on all channels. = no signal detected on one or more channels. O, LVCMOS Lock Indicator Output pin. H = PLL is locked. L = PLL is not locked. I, Analog I, Analog VOD control pin. Refer to Table 3. See Functional Description. External resistance k to GND, Output DC Coupled Application. External resistance k to GND, Output AC Coupled Application. Loop filter capacitor pins. See Functional Description.
Description VDD V ±5%. VDD pins should be tied to the VDD plane through a low inductance path. 0.1 µF bypass capacitor should be connected between each VDD pin to the GND planes. See Power Supply Bypassing for additional details. Ground reference. GND should be tied to a solid ground plane through a low impedance path. Ground reference. The exposed pad at the center of the package must be connected to the ground plane. Reserved. Do not connect. Leave open.
Ordering Information NSID DS34RT5110SQ DS34RT5110SQX Package 48 Lead LLP 48 Lead LLP 48 Lead LLP Tape & Reel QTY 1,000 2,500
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