|Category||Data Conversion => ADC (Analog to Digital Converters) => >14 bit => 16 bit|
|Description||Three Channel, 16-Bit, 81 MSPS Analog Front End With LVDS/CMOS Output And Integrated CCD/CIS Sensor Timing Generator
The LM98725 is a fully integrated, high performance 16-Bit, 81 MSPS signal processing solution for digital color copiers, scanners, and other image processing applications. High-speed signal throughput is achieved with an innovative architecture utilizing Correlated Double Sampling (CDS), typically employed with CCD arrays, or Sample and Hold (S/H) inputs (for higher speed CCD or CMOS image sensors). The signal paths utilize 8 bit Programmable Gain Amplifiers (PGA), a +/-9-Bit offset correction DAC and independently controlled Digital Black Level correction loops for each input. The PGA and offset DAC are programmed independently allowing unique values of gain and offset for each of the three inputs. The signals are then routed to a 81MHz high performance analog-to-digital converter (ADC). The fully differential processing channel shows exceptional noise immunity, having a very low noise floor of -74dB. The 16-bit ADC has excellent dynamic performance making the LM98725 transparent in the image reproduction chain
|Company||National Semiconductor Corporation|
|Datasheet||Download LM98725 datasheet
|Cross ref.||Similar parts: WM8199|
LM98725 3 Channel, 16-Bit, 81 MSPS Analog Front End with LVDS/CMOS Output Integrated Sensor Timing Generator and SSCG
LM98725 3 Channel, 16-Bit, 81 MSPS Analog Front End with LVDS/ CMOS Output, Integrated CCD/CIS Sensor Timing Generator and SSCG
The is a fully integrated, high performance 16-Bit, 81 MSPS signal processing solution for digital color copiers, scanners, and other image processing applications. Highspeed signal throughput is achieved with an innovative architecture utilizing Correlated Double Sampling (CDS), typically employed with CCD arrays, or Sample and Hold (S/H) inputs (for higher speed CCD or CMOS image sensors). The signal paths utilize 8 bit Programmable Gain Amplifiers (PGA), a +/-9-Bit offset correction DAC and independently controlled Digital Black Level correction loops for each input. The PGA and offset DAC are programmed independently allowing unique values of gain and offset for each of the three inputs. The signals are then routed a 81MHz high performance analog-to-digital converter (ADC). The fully differential processing channel shows exceptional noise immunity, having a very low noise floor of -74dB. The 16-bit ADC has excellent dynamic performance making the LM98725 transparent in the image reproduction chain. A very flexible integrated SSCG (Spread Spectrum Clock Generation) modulator is included to assist with EM compliance and reduce system costs.Features
LVDS/CMOS Outputs LVDS/CMOS/Crystal Clock Source with PLL Multiplication Integrated Flexible Spread Spectrum Clock Generation CDS or S/H Processing for CCD or CIS sensors Independent Gain/Offset Correction for Each Channel Automatic Gain and Offset for Each Channel Programmable Input Clamp Voltage Flexible CCD/CIS Sensor Timing Generator
Maximum Input Level or 2.4 Volt Modes (both with or - polarity option) ADC Resolution 16-Bit ADC Sampling Rate 81 MSPS INL +17/- 28 LSB (typ) Channel Sampling Rate 30/30/27 MSPS PGA Gain Steps 256 Steps PGA Gain Range to 8.3x Analog DAC Resolution +/-9 Bits Analog DAC Range or +/-614mV Digital DAC Resolution +/-6 Bits Digital DAC Range -2048 LSB + 2016 LSB SNR -74dB (@0dB PGA Gain) Power Dissipation 755mW (LVDS) Operating Temp to 70°C Supply Voltage 3.3V Nominal to 3.6V range)Applications
Multi-Function Peripherals Facsimile Equipment Flatbed or Handheld Color Scanners High-speed Document Scanner
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