|Category||Timing Circuits => Clock Buffers|
|Description||Quad Channel 26 MHz Clock Tree Driver With IC Interface
The LMH2190 is a quad channel configurable clock distribution device which supplies the system clock to peripherals in mobile handsets or other applications. It provides a solution to clocking issues such as drive capability for fanout or longer traces, protection of the master clock from varying loads and frequency pulling effects, isolation buffering from noisy modules, and crosstalk isolation. It has very low phase noise which enables it to drive sensitive modules such as Wireless LAN and Bluetooth.
The LMH2190 can be clocked up to 26 MHz, and has an independent clock request pin for each clock output which allows the peripheral to control the clock. It features an integrated LDO which provides an ultra low noise voltage supply with 10 mA external load current which can be used to supply the TCXO or other clock source.
|Company||National Semiconductor Corporation|
|Datasheet||Download LMH2190 datasheet
|Cross ref.||Similar parts: LMH2190TM-38/NOPB, STCD1040|
|LMH2190 Quad Channel 26 MHz Clock Tree Driver with I2C Interface
Quad Channel 26 MHz Clock Tree Driver with I2C Interface
The is a quad channel configurable clock distribution device which supplies the system clock to peripherals in mobile handsets or other applications. It provides a solution to clocking issues such as drive capability for fanout or longer traces, protection of the master clock from varying loads and frequency pulling effects, isolation buffering from noisy modules, and crosstalk isolation. It has very low phase noise which enables it to drive sensitive modules such as Wireless LAN and Bluetooth. The LMH2190 can be clocked to 26 MHz, and has an independent clock request pin for each clock output which allows the peripheral to control the clock. It features an integrated LDO which provides an ultra low noise voltage supply with 10 mA external load current which can be used to supply the TCXO or other clock source. The I2C serial interface can be used to override the default configuration of the device to optimize the LMH2190 for the application. Some of these programmable features include setting the polarity of both the clock and the clock request inputs. In addition, the clock outputs have programmable output drive current to optimize for the connected load. EMI switching noise can be controlled by configuring output drive and skew settings. The LMH2190 quad clock distributor is offered in a tiny 1.5mm 16 bump microSMD package. Its' small size and low supply current make it ideal for portable applications.Features
1 Input Clock, 4 Output Clocks Independent clock request Support both square or sine wave input Skewed clock outputs High isolation of supply noise to clock input High output to output Isolation Output Drive 50 pF EMI controlled output edges and EMI filtering Integrated Low-Dropout Regulator Low Output Noise Voltage 10 mA load current I2C Configurable to 400 kHz (Fast Mode) Ultra low standby current VBAT range to 5.5VApplications
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage VBAT - VSS LVCMOS port IO voltage ESD Tolerance (Note 2) Human Body Model Machine Model Charge Device Model Storage Temperature Range Junction Temperature (Note -0.3V to (VOUT to 150°C
Supply Voltage (VBAT - VSS) VENABLE Input Clock, SCLK_IN DC Mode AC Mode Duty Cycle Temperature Range Package Thermal Resistance JA (Note 3)
(Notes 4, 11) Unless otherwise specified, all limits are guaranteed = 25°C, VBAT = 3.5V, fSCLK_IN = 26 MHz, COUT = 2.2 µF, VDD_IO = 1.8V (See Block Diagram and (Note 9)), Registers are in default setting. Boldface limits apply at the temperature extremes. Symbol Parameter Condition Min (Note 6) Typ (Note 3 mA tbd A Max (Note 6) Units
Supply Current (Note 8) IDD Supply Current Clock outputs toggling at 26 MHz without external capacitors on CLK1/2/3/4, LDO is ON, IOUT = 0 mA. In Shutdown. No clocks toggling. LDO is OFF In Shutdown. Input CLK toggling, no Clock outputs toggling. LDO is OFF. IDDQ Quiescent Current No Clock outputs toggling. LDO is ON, IOUT = 0 mA. No Clock outputs toggling, LDO is ON, IOUT = 10 mA. IDDEN CPD Current to Enable pin Current to Enable pin Power Dissipation Capacitance per CLK output Propagation Delay SCLK_IN CLK1 - Low to High, Figure 1 (Note 7) Propagation Delay SCLK_IN CLK1 - High to Low, Figure 1 (Note 7) Skew Between Outputs (Either Edge), (Note 7) Rise Time, (Note 13) Fall Time, (Note 13) Output Clock Duty Cycle, Figure 3 (Note 7) I2C port is operational. I2C port is idle. Defined with respect to VOUT= 1.8V
CLK1 Additive Phase Noise with 100 Hz Output = 1 kHz = 10 kHz = 100 kHz = 1 MHz CLK2 Additive Phase Noise with 100 Hz Output = 1 kHz = 10 kHz = 100 kHz = 1 MHz CLK3 Additive Phase Noise with 100 Hz Output = 1 kHz = 10 kHz = 100 kHz = 1 MHz CLK4 Additive Phase Noise with 100 Hz Output = 1 kHz = 10 kHz = 100 kHz = 1 MHz
CLK1/2/3/4 Output Voltage High -2 mA Level CLK1/2/3/4 Output voltage Low Level SCLK_IN Input Voltage High Level SCLK_IN Input Voltage Low Level SCLK_IN Input Current High Level SCLK_IN Input Current Low Level Input Capacitance (Note 7) DC Bias Voltage Input Resistance AC Mode AC Mode, Clock path enabled. 2 mA
System Clock Input (SCLK_IN) VIH DC Mode AC Mode VIL DC Mode AC Mode IIH IIL CIN VBIAS RIN SCLK_IN = 1.8V, Clock path disabled SCLK_IN = VSS, Clock path disabled 0.65 x VDD_IO tbd 0.35 x VDD_IO 0.6 +1 tbd k V
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