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Details, datasheet, quote on part number: MPS14
 
 
Part numberMPS14
Category
TitleMPS14 Dual-PLL Precision Any Frequency Synthesizer
DescriptionThe MPS14 is a dual-PLL programmable synthesizer intended for jitter attenuation and asynchronous clocking applications in high performance telecommunications, networking, data storage, SERDES and PHY applications. The device incorporates two low jitter PLLs that provide any frequency up to 938MHz with precision better than 0.1ppb. Each PLL integrates a 1:2 fanout buffer with integer dividers and mix-and-match programmable outputs that provide LVPECL/LVDS/HCSL/CMOS output formats, delivering maximum flexibility and jitter performance in a compact 7x7mm 48-pin QFN package.



Each output is independently programmable to provide frequencies up to 938 MHz with 266fs to 450fs RMS jitter (12KHz to 20MHz) utilizing compact, low cost fundamental mode XTALs that enable a robust supply chain. Using optional integer frequency synthesis, the MPS14 is capable of achieving jitter as low as 225fs.



The MPS14 DigiPull functionality enables numerically controlled frequency pulling applications using the fast SPI bus. FPGAs and other devices can take advantage of this function to implement digital PLLs with configurable loop bandwidths for jitter attenuation applications, precision disciplined clocks that lock to tight stability references or digitally controlled precision timing applications such as network timing, timing over packet and IEEE1588 applications. The SPI bus operates up to 6MHz, enabling fast FPGA loops while multiple devices share the same bus. Multi-rate precision applications such as broadcast video or OTN can also use the MPS14. HDL FPGA code for digital PLL applications available from Multigig.
CompanyMultigig, Inc.
DatasheetDownload MPS14 datasheet
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Specifications, Features, Applications
Features
· Any frequency precision synthesis · Ultra-low RMS jitter to 20 MHz) ·

The is a programmable synthesizer intended for jitter attenuation and asynchronous clocking applications in high performance telecommunications, networking, data storage, SERDES and PHY applications. The device incorporates two low jitter PLLs that provide any frequency with precision better than 0.1ppb, integrated 1:2 fanout buffers with integer division capability and mix-and-match programmable output formats, delivering maximum flexibility and jitter performance. Each output is independently programmable to provide frequencies to 938 MHz with to 450fs typical RMS jitter to 20MHz) utilizing compact, low cost fundamental mode XTALs that enable a robust supply chain. Using optional integer frequency synthesis, the MPS14 is capable of achieving jitter as low as 225fs. The MPS14 ships with a factory programmed default poweron configuration. After power-on, all settings including output frequency are reconfigurable through a fast SPI interface. The MPS14 DigiPull functionality enables numerically controlled frequency pulling applications using the fast SPI bus. FPGAs and other devices can take advantage of this function to implement digital PLLs with configurable loop bandwidths for jitter attenuation applications, precision disciplined clocks that lock to tight stability references or digitally controlled precision timing applications such as network timing, timing over packet and IEEE1588 applications. The SPI bus can operate to 6MHz, enabling fast FPGA loops while multiple devices share the same bus.The MPS14 can also be used in multi-rate precision applications such as broadcast video or OTN. HDL FPGA code for digital PLL applications available from Multigig.

· 12 MHz to 938 MHz (V speed grade)· Better than 0.1ppb resolution· 225fs using integer synthesis· to 450fs using fracional synthesis· to 54 MHz fundamental, non-pullable· XTAL packages from 2.5x2.0mm· Dynamically pullable output frequency enables

Supports low cost and compact XTALs DigiPull numerical frequency control

Dual PLL in compact 7x7mm package · Replaces multiple large clock ICs, PLLs, fanout buffers, XOs, and VCXOs Mix-and-match output buffers

· Independent buffer VDDO drives multiple technologies Enhanced VDD noise rejection
Applications

· FPGA-based jitter attenuator and low jitter PLL Precision-disciplined clock and clock synthesizer Multi-rate clock synthesizer Optical: OTN/SDH/SONET Broadcast video: 3G SDI, HD SDI, SDI Networking and storage: Ethernet/SAS/Fiberchannel Wireless infrastructure: OBSAI/CPRI Industrial: IEEE1588 Numerically controlled oscillators (NCO)

Multigig, Inc. 2645 Zanker Road, Suite 101, San Jose, CA. 95134 MPS14B Revision: 0.992, July, 2011

Pin # REFIN OUT1 48 QFN Pin Name Reference Clock Input Crystal Input Reference Input Select 1 Reference Input Select 2 Clock Output 1 Type INPUT Selectable1 INPUT Passive INPUT LVCMOS INPUT LVCMOS OUTPUT Selectable1 Description External Reference Clock Input. Can be selected as the reference clock for PLL1, PLL2, and/or the Reference Clock Output

External Crystal should be connected to these pins to drive the internal oscillator reference. The Crystal Reference/Oscillator Input can be used as the reference for PLL1, PLL2 and/or the Reference Clock Output. Reference Select 1 selects the input source for PLL1. Either the External Crystal or External Reference In can be selected. Reference Select 2 selects the input source for PLL2. Either the External Crystal or External Reference In can be selected.

Clock Output derived from PLL1. Supports frequencies up to the device maximum. When used in LVCMOS mode, OUT1 is the active pin. OUT1 is not used and is High-Z.