Details, datasheet, quote on part number: S71KL512SC0BHV000
PartS71KL512SC0BHV000
Category
TitleIC 512MB FLASH 64MB DRAM 24FBGA
Description

The Cypress HyperFlash™ and HyperRAM™ multi-chip package (MCP) is a solution that combines a high-speed NOR Flash memory for fast-boot, instant-on capability with a self-refresh DRAM for expanded scratchpad memory in a reduced footprint, (measuring 8 mm by 6 mm) low-pin-count package in a 24 BGA. This complete NOR Flash/DRAM memory subsystem, based on the Cypress HyperBus™ interface, is the ideal solution for space-constrained and cost-optimized IoT and embedded designs.



CompanyCypress Semiconductor Corp.
DatasheetDownload S71KL512SC0BHV000 datasheet
  
S71KL512SC0BHV000 photo

 

Features, Applications

HyperFlash and HyperRAM in Multi-Chip Package (MCP) 512 Mb HyperFlash and 64 Mbit HyperRAM (S71KL512SC0) FBGA 1.0 mm package HyperBus Interface 3.0V I/O, 11 bus signals Single ended clock (CK) Chip Select (CS#) 8-bit data bus (DQ[7:0]) Read-Write Data Strobe (RWDS) Bidirectional Data Strobe/Mask Output at the start of all transactions to indicate refresh latency Output during read transactions as Read Data Strobe Input during write transactions as Write Data Mask

Optional Signals Reset INT# output to generate external interrupt Busy to Ready Transition RSTO# Output to generate system level Power-On Reset (POR) User configurable RSTO# Low period High Performance Double-Data Rate (DDR) Two data transfers per clock to 100-MHz clock rate (200 MB/s) at 3.0 VCC

Cypress Semiconductor Corporation Document Number: 002-03902 Rev. *B

General Description......................................................... 3 HyperBus MCP Family with HyperFlash and HyperRAM................................. 3 HyperBus MCP 3V Signal Descriptions.......................... 4 HyperBus MCP Block Diagram................................... 5 Physical Interface............................................................. 6 HyperBus MCP FBGA 24-Ball, 5x5 Array Footprint...................................................... 6 Physical Diagram........................................................ 7 Electrical Specifications.................................................. 8 Absolute Maximum Ratings......................................... 8 DC Characteristics...................................................... 8 Ordering Part Numbers.................................................. 11 Valid Combinations Standard............................... 11 Valid Combinations Automotive Grade AEC-Q100................................. 12 Document History Page................................................. 13 Sales, Solutions, and Legal Information...................... 14 Worldwide Sales and Design Support....................... 14 Products.................................................................... 14 PSoC Solutions...................................................... 14 Cypress Developer Community................................. 14 Technical Support..................................................... 14

This supplementary datasheet provides MCP device related information for a HyperBus MCP family, incorporating both HyperFlash and HyperRAM memories. The document describes how the features, operation, and ordering options of the related memories have been enhanced or changed from the standard memory devices incorporated in the MCP. The information contained in this document modifies any information on the same topics established by the documents listed in Table 1 and should be used in conjunction with those documents. This document may also contain information that was not previously covered by the listed documents. The information is intended for hardware system designers and software developers of applications, operating systems, or tools. Table 1. Affected Documents/Related Documents Title HyperBusTM Specification Low Signal Count, High Performance DDR Bus S26KS128S, 512 MBIT (64 MBYTE), 256 Mbit (32 Mbyte), 128 Mbit (16 Mbyte) 1.8V/3.0V HyperFlashTM Family S27KL0641, S27KS0641: HyperRAMTM Self-Refresh DRAM 3.0V/1.8V 64 Mbit (8 Mbyte) Cypress Publication Number 001-99198 001-97964

For systems needing both Flash and self-refresh DRAM, the HyperBus products family includes MCP devices that combine HyperFlash and HyperRAM in a single package. A HyperBus MCP reduces board space and Printed Circuit Board (PCB) signal routing congestion while also maintaining or improving signal integrity over separately packaged memory configurations. The HyperBus MCP family offers 3V interface HyperFlash densities Mb (64 MB) in combination with HyperRAM Mb (8 MB). This supplemental datasheet addresses only the MCP related differences from the HyperBus Specification and the individual HyperFlash and HyperRAM datasheets. For all other information related to the individual memories in the MCP, refer to the HyperBus, HyperFlash, and HyperRAM datasheets.


 

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