Details, datasheet, quote on part number: DRV8701PRGET
PartDRV8701PRGET
CategorySemiconductors => Motor Drivers => Brushed DC (BDC) Drivers => Brushed DC Gate Drivers
Part familyDRV8701 Brushed DC Motor Gate Driver (PH/EN, PWM Ctrl)
TitleIC MOTOR GATE DVR DC 24VQFN
DescriptionBrushed DC Motor Gate Driver (PH/EN, PWM Ctrl) 24-VQFN -40 to 125
CompanyTexas Instruments Inc.
StatusACTIVE
ROHSCompliant
SampleYes
DatasheetDownload DRV8701PRGET datasheet
Specifications 
Control I/FPHASE/ENABLE, PWM
RatingCatalog
Additional FeaturesAdjustable gate drive settings, 3.3V/5V LDO, integrated current shunt amplifier, low-power sleep mode
Peak Output Sink Current Gate Drive(Max)(A)0.3
Peak Output Source Current Gate Drive(Max)(A)0.15
Vs(Min)(V)5.9
Vs(Max)(V)45
Approx. Price (US$)0.92 | 1ku
  Mecanical Data
Pin nbPackage typeInd stdJEDEC codePackage qtyCarrierDevice markWidth (mm)Length (mm)Thick (mm)Pitch (mm)
24RGEVQFNS-PQFP-N250SMALL T&R8701P 44.88.5
Application notes
• Understanding TDRIVE and IDRIVE In TI Motor Gate Drivers (Rev. A)
The motor gate driver is an integrated circuit (IC) that primarily deals with enhancing external power MOSFETs to drive an electric motor. The gate driver acts as an intermediate stage between the logic-level control inputs and the power MOSFETs. The gate | Doc
Evaluation Kits
DRV8701EVM: DRV8701 Full Bridge Brushed DC Motor Gate Driver Evaluation Module
Spice Model
DRV8701E PSpice Transient Model - ZIP (03/20/2015)
DRV8701 TINA-TI Transient Spice Model - ZIP (08/13/2015)

Others parts numbering
DRV8701ERGET
DRV8701EVM: EVALUATION MOD DRV8701

 

Features, Applications

Industrial Brushed-DC Motors Robotics Home Automation Industrial Pumps and Valves Power Tools Handheld Vacuum Cleaners

Single H-Bridge Gate Driver Drives Four External N-Channel MOSFETs Supports 100% PWM Duty Cycle to 45-V Operating Supply Voltage Range Two Control Interface Options PH/EN (DRV8701E) PWM (DRV8701P) Adjustable Gate Drive (5 Levels) to 150-mA Source Current to 300-mA Sink Current Supports 1.8-V, 3.3-V, and 5-V Logic Inputs Current Shunt Amplifier (20 V/V) Integrated PWM Current Regulation Limits Motor Inrush Current Low-Power Sleep Mode (9 A) Two LDO Voltage Regulators to Power External Components AVDD: to 30-mA Output Load DVDD: to 30-mA Output Load Small Package and Footprint 24-Pin VQFN (PowerPADTM) mm Protection Features: VM Undervoltage Lockout (UVLO) Charge Pump Undervoltage (CPUV) Overcurrent Protection (OCP) Pre-Driver Fault (PDF) Thermal Shutdown (TSD) Fault Condition Output (nFAULT)

The is a single H-bridge gate driver that uses four external N-channel MOSFETs targeted to drive to 24-V bidirectional brushed DC motor. A PH/EN (DRV8701E) or PWM (DRV8701P) interface allows simple interfacing to controller circuits. An internal sense amplifier allows for adjustable current control. The gate driver includes circuitry to regulate the winding current using fixed off-time PWM current chopping. DRV8701 drives both high- and low-side FETs with 9.5-V VGS gate drive. The gate drive current for all external FETs is configurable with a single external resistor on the IDRIVE pin. A low-power sleep mode is provided which shuts down internal circuitry to achieve very-low quiescent current draw. This sleep mode can be set by taking the nSLEEP pin low. Internal protection functions are provided: undervoltage lockout, charge pump faults, overcurrent shutdown, short-circuit protection, predriver faults, and overtemperature. Fault conditions are indicated on the nFAULT pin. Device Information(1)

PART NUMBER DRV8701 PACKAGE VQFN (24) BODY SIZE (NOM) 0.90 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
PH/EN or PWM nSLEEP VREF Controller sense output nFAULT

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

Features.................................................................. Applications........................................................... Description............................................................. Revision History..................................................... Pin Configuration and Functions......................... Specifications.........................................................

Absolute Maximum Ratings...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information.................................................. Electrical Characteristics........................................... Typical Characteristics..............................................

7.1 Overview................................................................. 12 7.2 Functional Block Diagram....................................... 13 7.3 Feature Description................................................. 14

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (May 2015) to Revision B Page

Updated test conditions for IDRIVE,SNK and corrected TYP values........................................................................................... 8 Page

Submit Documentation Feedback Product Folder Links: DRV8701
RGE Package 24-Pin VQFN DRV8701E Top View RGE Package 24-Pin VQFN DRV8701P Top View
DESCRIPTION
TYPE Input Bridge enable input Bridge phase input

Logic low places the bridge in brake mode; see Table 1 Controls the direction of the H-bridge; see Table 1

PIN NAME IN1 IN2 NO. 15 14 TYPE Input Bridge PWM input DESCRIPTION Logic controls the state of H-bridge; see Table 2

PIN NAME VM NO. 1 5 GND VCP CPH CPL DVDD AVDD nSLEEP IDRIVE 16 PPAD Power Input Charge pump output Charge pump switching nodes Logic regulator Analog regulator Device sleep mode Gate drive current setting pin Connect 16-V, 1-F ceramic capacitor to VM Connect 0.1-F X7R capacitor rated for VM between CPH and CPL 3.3-V logic supply regulator; bypass to GND with 6.3-V, 1-F ceramic capacitor 4.8-V analog supply regulator; bypass to GND with 6.3-V, 1-F ceramic capacitor Pull logic low to put device into a low-power sleep mode with FETs High-Z; internal pulldown Resistor value or voltage forced on this pin sets the gate drive current; see applications section for more details Power Device ground Must be connected to ground TYPE DESCRIPTION Connect to motor supply voltage; bypass to GND with a 0.1-F ceramic plus a 10-F minimum capacitor rated for VM; additional capacitance may be required based on drive current


 

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