|Title||IC MCU 8BIT 7KB FLASH 14SOIC|
|Company||Genesis Microchip Inc.|
|Datasheet||Download PIC16F15324-I/SL datasheet
|Others parts numbering|
|PIC16F15324-I/ST: IC MCU 8BIT 7KB FLASH 14TSSOP|
|PIC16F15324-I/JQ: IC MCU 8BIT 7KB FLASH 16UQFN|
|PIC16F15344-I/SS: IC MCU 8BIT 7KB FLASH 20SSOP|
|PIC16F15324-I/P: IC MCU 8BIT 7KB FLASH 14DIP|
This programming specification describes an SPI-compatible programming method for the PIC16(L)F153XX family of microcontrollers. Section 3.0 "Programming Algorithms" describes the programming commands, programming algorithms and electrical specifications which are used in that particular programming method. Appendix B contains individual part numbers, device identification and checksum values, pinout and packaging information, and Configuration Words. Note: To enter LVP mode, the MSb of the Most Significant nibble must be shifted in first. This differs from entering the key sequence on some other device families.
Nonvolatile Memory (NVM) programming data can be supplied by either the high-voltage In-Circuit Serial ProgrammingTM (ICSPTM) interface or the low-voltage In-Circuit Serial Programming (ICSP) interface. Data can be programmed into the Program Flash Memory (PFM), (EEPROM, if available), dedicated "User ID" locations and the Configuration Words.
Erasing or writing is selected according to the command used to begin operation (see Table 3-1). The terminologies used in this document related to erasing/writing to the Program Flash Memory are defined in Table 1-1 and are detailed below.
Term Definition A memory cell with a logic `0' A memory cell with a logic `1' Change memory cell from a `1' Change memory cell from a `0' Generic erase and/or writeProgrammed Cell Erased Cell Erase Write Program
Program Flash Memory is erased by row or in bulk, where `bulk' includes many subsets of the total memory space. The duration of the erase is always determined internally. Here, `row' refers to the minimum erasable size and `bulk' is one of the many possible subsets of all memory rows. All Bulk ICSP Erase commands have minimum VDD requirements, which are higher than the Row Erase and write requirements. Refer to Section 3.5 "Electrical Specifications".
Program Flash Memory is written one row at a time. Multiple load data for NVM commands are used to fill the row data latches. The duration of the write is determined either internally or externally. Refer to Section 3.5 "Electrical Specifications".
Program Flash Memory (PFM) panels include a 32-word (one row) programming interface. The row to be programmed must first be erased either with a Bulk Erase or a Row Erase. Refer to Section 3.5 "Electrical Specifications".
In High-Voltage ICSP mode, the device requires two programmable power supplies: one for VDD and one for the MCLR/ VPP pin.
In Low-Voltage ICSP mode, the device can be programmed using a single VDD source in the operating range. The MCLR/VPP pin does not have to be brought to a different voltage, but can instead be left at the normal operating voltage.
The LVP Configuration bit enables single-supply (low-voltage) ICSP programming. The LVP bit defaults a `1' (enabled) from the factory. The LVP bit may only be programmed `0' by entering the High-Voltage ICSP mode, where the MCLR/VPP pin is raised to VIHH. Once the LVP bit is programmed a `0', only the High-Voltage ICSP mode is available and only the High-Voltage ICSP mode can be used to program the device. Note 1: The High-Voltage ICSP mode is always available, regardless of the state of the LVP bit, by applying VIHH to the MCLR/VPP pin. 2: While in Low-Voltage ICSP mode, MCLR is always enabled, regardless of the MCLRE bit, and the port pin can no longer be used as a general purpose input.
Five pins are needed for ICSP programming. The pins are listed in Table 1-2. Refer to Table B-2 for pin locations and packaging information.
During Programming Function Pin Type I I/O I(1) P Pin Description Clock Input Schmitt Trigger Input Data Input/Output Schmitt Trigger Input Program Mode Select Power Supply Ground
Legend: I = Input, O = Output, P = Power Note 1: The programming high voltage is internally generated. To activate the Program/Verify mode, high voltage needs to be applied to the MCLR input. Since the MCLR is used for a level source, MCLR does not draw any significant current.
0000h Program Flash Memory 821Fh 8220h User IDs(2) Reserved Revision ID(2,3) Device ID(2,3) Configuration Word 1,2,3,4,5(2) Program Flash Memory Program Flash Memory Program Flash MemoryReserved Device Information Area(2) Reserved Device Configuration Information(2,3)
FFFFh Note The stack is a separate SRAM panel, apart from all user memory panels. Not code-protected. Device Configuration Information, Device/Revision IDs are hard-coded in silicon. The addresses do not roll over. The region is read as `0'. For the purposes of instruction fetching during program execution, only 15 bits (PC<14:0>) are used. However, for the purposes of nonvolatile memory reading and writing through ICSPTM programming operations, the PC uses all 16 bits (PC<15:0>), and the "Load PC Address" command requires a full 16-bit data payload.
|Some Part number from the same manufacture Genesis Microchip Inc.|