Details, datasheet, quote on part number: MAX14001AAP+
PartMAX14001AAP+
Category
TitleIC ADC 10BIT 10KSPS 20-SSOP
Description
CompanyMaxim Integrated Products
DatasheetDownload MAX14001AAP+ datasheet
  
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MAX14001EVSYS: EVAL FOR MAX14001

 

Features, Applications

Configurable, Isolated 10-bit ADCs for Multi-Range Binary Inputs

The MAX14001/MAX14002 are isolated, single-channel analog-to-digital converters (ADCs) with programmable voltage comparators and inrush current control optimized for configurable binary input applications. 3.75kVRMS of integrated isolation is provided between the binary input side (field-side) and the comparator output/SPI-side (logic-side) of the MAX14001/MAX14002. An integrated, isolated, DC-DC converter powers all field-side circuitry, and this allows running field-side diagnostics even when no input signal is present. The 20-pin SSOP package provides 5.5mm of creepage and clearance with group II CTI rating. These devices continually digitize the input voltage on the field-side of an isolation barrier and transmit the data across the isolation barrier to the logic-side of the device where the magnitude of the input voltage is compared to programmable thresholds. The binary comparator output pin is high when the input voltage is above the upper threshold and low when it is below the lower threshold. Response time of the comparator to an input change is less than 150s with filtering disabled. With filtering enabled, the comparator uses the moving average of the last or 8 ADC readings. Both filtered and unfiltered ADC readings are available through the 5MHz SPI port, which is also used to set comparator thresholds and other device configuration. The MAX14001/MAX14002 control the current of a binary input through an external, high-voltage FET. This current cleans relay contacts and attenuates input noise. An inrush comparator monitoring the ADC readings triggers the inrush current, or wetting pulse. The inrush trigger threshold, current magnitude, and current duration are all programmable in the MAX14001 but are fixed in the MAX14002. When the high-voltage FET is not providing inrush current, it switches to bias mode. Bias mode places a small current load on the binary input to attenuate capacitively coupled noise. The level of bias current is programmable between 50A and 3.75mA in both the MAX14001 and MAX14002. This allows optimization of the tradeoff between noise attenuation and power dissipation.

Enables Robust Detection of Binary Inputs Programmable Input Bias Current Rejects Line Noise 3.75kVRMS of Isolation for 60 Seconds 5.5mm of Creepage and Clearance Group II CTI Package Material Reduces BOM and Board Space Through High Integration 10-bit, 10ksps ADC Binary Threshold Comparators Control Circuit for Driving a Depletion Mode FET Isolation for Both Data and DC-DC Supply 20-SSOP Package Increases Equipment "Up Time" and Simplifies System Maintenance Enables Field-Side Diagnostics Automatic Self-Diagnostics Provides Unparalleled Flexibility Programmable Upper and Lower Input Thresholds Programmable Inrush Current Activation Threshold, Magnitude, and Duration Daisy-Chainable SPI Interface

Applications

High-Voltage Binary Input (12V300V) Distribution Automation Substation Automation Industrial Control, Multi-Range, Digital Input Modules with Individually Isolated Inputs

VDDL to +6V VDD to +6V Logic-Side Inputs (CS, SCLK, SDI, FAULT) to GNDL................................................................................. to +6V Logic-Side Outputs (SDO, COUT) to GNDL............................................... -0.3V to (VDDL + 0.3V) VREFIN, VAIN to +2V AGND to +0.3V GATE to +4V IFET to +12V ISET to +2V VDDF to +6V Short-Circuit Duration (FAULT, COUT, SDO to GNDL or VDD).................Continuous Continuous Power Dissipation (TA 20-pin SSOP...............................................................952.4mW Operating Temperature Range.......................... to +125C Junction Temperature.......................................................+150C Storage Temperature Range............................. to +150C Lead Temperature (soldering, 10s).................................. +300C Soldering Temperature (reflow)........................................+260C

Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

20-pin SSOP Junction-to-Ambient Thermal Resistance (JA)...........84C/W Junction-to-Case Thermal Resistance (JC)................32C/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

(VDDL - VGNDL to 5.5V, VDD - VGNDL to 3.6V, RISET to +125C, VGNDF = VGNDL. Typical values are = +25C with VDDL = VDD = +3.3V, RISET = 120k, VGNDF = VGNDL.) (Notes 2, 3) PARAMETER POWER SUPPLIES Logic Power Supply Logic Supply Current Isolated DC-DC Power Supply Input Voltage Isolated DC-DC Supply Input Current Logic Power-Up Delay Field Power-Up Delay Field Power Supply Gate Charge Pump Voltage Logic-Side Undervoltage Lockout Threshold Logic-Side Undervoltage Lockout Threshold Hysteresis Field-Side Undervoltage Lockout Threshold VDDF VGATE VUVLOL VUVLOD VUVLHYST VUVDHYST VUVLOF (Note 4) 1.95 CVDDF = 0.1F CVDDF = 0.1F, unregulated output voltage 1A pull-down VDD 3V VDDL 1.71V VDDL IDDL VDD IDD VDDL 3.3V, no load, CS = high VDD mV V SYMBOL CONDITIONS MIN TYP MAX UNITS

(VDDL - VGNDL to 5.5V, VDD - VGNDL to 3.6V, RISET to +125C, VGNDF = VGNDL. Typical values are = +25C with VDDL = VDD = +3.3V, RISET = 120k, VGNDF = VGNDL.) (Notes 2, 3) PARAMETER Field-Side Undervoltage Lockout Threshold Hysteresis PROTECTION ESD EFT (Burst) DYNAMIC Common-Mode Transient Immunity ADC AND COMPARATOR Input Voltage Range Reference Input Range ADC Resolution Gain Error Offset Error Differential Nonlinearity Integral Nonlinearity Input Leakage Current Throughput Latency (No Filtering) Latency (2 Readings) Latency (4 Readings) Latency (8 Readings) Nominal Output Voltage Output Voltage Accuracy Output Voltage Temperature Drift Reference Voltage Available Bias Current TCVOUT VAIN VREFIN GE OE DNL INL IILR AIN step input to COUT transition (Notes 4, 7) AIN step input to COUT transition (Notes 4, 7) AIN step input to COUT transition (Notes 4, 7) AIN step input to COUT transition (Notes 4, 7) Over the entire temperature range Included in the gain + offset window VAIN = 1.25V Nominal measurement range VIN = 98% VREF, excluding offset error and reference errors VIN = 2% VREF, offset calculated VREFIN V Bits % %FS LSB nA ksps V % ppm/C CMTI (Note 6) 50 kV/s Any pin to GNDL or GNDF inclusive System-level requirement IEC 61000-4-4 common mode (Note 3 kV SYMBOL VUVFHYST CONDITIONS MIN TYP 100 MAX UNITS mV

EXTERNAL VOLTAGE REFERENCE When powered from VDDF (series) or REFIN (shunt) V A

 

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