|Title||EVAL KIT ADUCM3027 ADUCM3029|
|Datasheet||Download ADZS-UCM3029EZLITE datasheet
|Others parts numbering|
|ADUCM3027BCPZ: CORTEXM3 W/128KEMBEDDED FLASH/AD|
|ADUCM3029BCPZ: CORTEX M3W/256KEMBEDDED FLASH/AD|
|ADUCM3027BCPZ-R7: CORTEXM3 W/128KEMBEDDED FLASH/AD|
|ADUCM3029BCPZ-RL: CORTEX M3W/256KEMBEDDED FLASH/AD|
|Silicon Anomaly List ABOUT ADuCM3027/9 SILICON ANOMALIES
Ultra Low Power ARM Cortex-M3 MCU with Integrated Power Management ADuCM3027/9
These anomalies represent the currently known differences between revisions of the ADuCM3027/9 product(s) and the functionality specified in the ADuCM3027/9 data sheet(s) and the Hardware Reference book(s).
A silicon revision number with the form "-x.x" is branded on all parts. The silicon revision can be electronically determined by reading bits <3:0> of the SYS_CHIPID register.
The following revision history lists the anomaly list revisions and major changes for each anomaly list revision.
Date 03/03/2017 Anomaly List Revision D Data Sheet Revision 0 Additions and Changes Removed Silicon Revision 1.0 Added Silicon Revision 1.2 Added Anomalies: 21000016, 21000017 Removed Anomaly: 21000012 Removed Deprecated Part Numbers ADuCM3023/5 Initial Version
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The following table provides a summary of ADuCM3027/9 anomalies and the applicable silicon revision(s) for each anomaly.
No. ID Description I2C Master Mode Fails to Generate Clock when Clock Dividers Are Too Small Pin P2_11 Is Not Retained After Shutdown Wake Up Possible Receive Data Loss with I2C Automatic Clock Stretching SPI Read Command Mode Does Not Work Properly When SPI_CNT Is 1 and DMA Is Enabled Rev 1.2Silicon Anomaly List DETAILED LIST OF SILICON ANOMALIES
The following list details all known silicon anomalies for the ADuCM3027/9 including a description, workaround, and identification of applicable silicon revisions.- I2C Master Mode Fails to Generate Clock when Clock Dividers Are Too Small:
When the I2C clock dividers are configured in Master mode such that the sum of the I2C_DIV.LOW and I2C_DIV.HIGH register bit fields is less than 16, the I2C fails to generate a clock.The state of pin P2_11 is not retained after waking up from shutdown mode.
None. To retain the pin state through shutdown, use any other GPIO pin instead of P2_11.
21000016 - Possible Receive Data Loss with I2C Automatic Clock Stretching:
When the I2C RX FIFO is full and new I2C data is received, a data overflow occurs. When automatic clock stretching is enabled, the transaction is paused by holding the SCL line low. This functions as expected when the next read happens after the clock is stretched (i.e., after the overflow is detected); however, if the read occurs after the last bit of the I2C data is received but before the clock is stretched, the received data is not written to the RX FIFO and is lost.
To avoid waiting for the lost data, use the timeout feature when enabling automatic clock stretching. Configure I2C_ASTRETCH_SCL.SLV (for slave mode) and I2C_ASTRETCH_SCL.MST (for master mode) with values between 1 and 14. Identify the data loss = 1) and request for data retransmission.
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