Details, datasheet, quote on part number: DLPC4422ZPC
PartDLPC4422ZPC
CategorySemiconductors => DLP Products => Display & Projection => Standard Chipsets
Part familyDLPC4422 DLP® Display Controller
TitleDisplay Drivers & Controllers
DescriptionDLP® Display Controller 516-BGA
CompanyTexas Instruments Inc.
StatusACTIVE
ROHSNot Compliant
SampleYes
DatasheetDownload DLPC4422ZPC datasheet
Specifications 
Product CategoryDisplay Drivers & Controllers
ManufacturerTexas Instruments
SeriesDLPC4422
ProductDisplay Controllers
Display TypeUHD
Operating Supply Voltage-
Maximum Operating Temperature-
Mounting StyleSMD/SMT
Package/CasePGBA-516
PackagingTray
BrandTexas Instruments
Operating Frequency20 MHz
Factory Pack Quantity1
TypeDLP Display Controller
  Mecanical Data
Pin nbPackage typeInd stdJEDEC codePackage qtyCarrierDevice markWidth (mm)Length (mm)Thick (mm)Pitch (mm)
48DLP1JEDEC TRAY (10+1)
Application notes
• TI DLP® System Design: Brightness Requirements and Tradeoffs (Rev. A) | Doc

 

Features, Applications

Provides Two 30-bit Input Pixel Interfaces or One 60-bit Input Pixel Interface: ­ YUV, YCrCb, or RGB Data Format or 10 Bits per Color ­ Pixel Clock Support to 175 MHz for 30-bit and 160 MHz for 60-bit Supports 24-30 Hz and 47-120 Hz Frame Rates Full Single DLP Controller Support For DMDTMs to 1920 Pixels Wide Dual DLP Controller Support For to 4K Ultra High Definition (UHD) Resolution Display Using DLP660TE TRP DMD High-Speed, Low Voltage Differential Signaling (LVDS) DMD Interface 150 MHz ARM946TM Microprocessor Peripherals ­ Programmable Pulse-Width Modulation (PWM) and Capture Timers ­ Three I2C Ports, Three UART Ports and Three SSP Ports ­ One USB 1.1 Slave Port Image Processing ­ Multiple Image Processing Algorithms ­ Frame Rate Conversion ­ Color Coordinate Adjustment ­ Programmable Color Space Conversion ­ Programmable Degamma and Splash ­ Integrated Support for 3-D Display On-Screen Display (OSD) Integrated Clock Generation Circuitry

­ Operates on a Single 20 MHz Crystal ­ Integrated Spread Spectrum Clocking External Memory Support ­ Parallel Flash for Microprocessor and PWM Sequence ­ Optional SRAM 516 Pin Plastic Ball Grid Array Package Supports Lamp, LED, and Laser Hybrid Illumination Systems

4K Ultra High Definition (UHD) Display Laser TV Digital Signage Projection Mapping

is a digital display controller for the DLP 4K UHD display chipset. The DLPC4422 display controller, together with the DLP660TE DMD and DLPA100 power management and motor driver device, comprise the chipset. This solution is a great fit for display systems that require high resolution, high brightness and system simplicity. To ensure reliable operation, the DLPC4422 display controller must always be used with the DLP660TE DMD and the DLPA100 power management and motor driver device. Device Information(1)

PART NUMBER DLPC4422 PACKAGE ZPC (516) BODY SIZE (NOM) 27.00 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

Absolute Maximum Ratings.................................... 14 ESD Ratings............................................................ 14 Recommended Operating Conditions..................... 15 Thermal Information................................................ 15 Electrical Characteristics......................................... 16 System Oscillators Timing Requirements............... 18 Test and Reset Timing Requirements.................... 18 JTAG Interface: I/O Boundary Scan Application Timing Requirements............................................... 19 6.9 Port 1 Input Pixel Timing Requirements................. 19 6.10 Port 3 Input Pixel Interface (via GPIO) Timing Requirements........................................................... 20 6.11 DMD LVDS Interface Timing Requirements......... 21 6.12 Synchronous Serial Port (SSP) Interface Timing Requirements........................................................... 21 6.13 Programmable Output Clocks Switching Characteristics......................................................... 22 6.14 Synchronous Serial Port Interface (SSP) Switching Characteristics......................................................... 22 6.15 JTAG Interface: I/O Boundary Scan Application Switching Characteristics......................................... 23

7.1 Overview................................................................. 27 7.2 Functional Block Diagram....................................... 27 7.3 Feature Description................................................. 27

System Power Regulations..................................... System Power-Up Sequence.................................. Power-On Sense (POSENSE) Support.................. System Environment and Defaults..........................

Submit Documentation Feedback Product Folder Links: DLPC4422

 

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