Details, datasheet, quote on part number: ADSP-21489
PartADSP-21489
Category
TitleHigh Performance Fourth Generation DSP
DescriptionThe SHARC ADSP-21489 is one of two new members of the fourth generation of SHARC® Processors, that now includes the ADSP-21483, ADSP-21486, ADSP-21487, ADSP-21488, ADSP-21489 and offers increased performance, hardware-based filter accelerators, audio and application-focused peripherals, and new memory configurations capable of supporting the latest surround-sound decoder algorithms. All devices are pin-compatible with each other and completely code-compatible with all prior SHARC Processors. These newest members of the fourth generation SHARC Processor family are based on a single-instruction, multiple-data (SIMD) core, which supports both 32-bit fixed-point and 32-/40-bit floating-point arithmetic formats making them particularly suitable for high-performance audio applications.

The ADSP-21489 offers the highest performance – 450 MHz / 2700 MFLOPs – in an LQFP package within the fourth generation SHARC Processor family. This level of performance makes the ADSP-21489 particularly well suited to address the automotive audio and industrial control segments. In addition to its high core performance, the ADSP-21489 includes additional processing blocks such as FIR, IIR, and FFT accelerators to increase the total performance of the system. There is a new feature called Variable Instruction Set Architecture (VISA) that allows the code size to be decreased by 20% to 30% and increase the memory size availability. The fourth generation DSP allows the ability to connect to external memory by providing a glueless interface to 16-bit wide SDR SDRAMs.
CompanyAnalog Devices
DatasheetDownload ADSP-21489 datasheet
  
ADSP-21489 photo

 

Features, Applications
FEATURES

High performance 32-bit/40-bit floating-point processor optimized for high performance audio processing Single-instruction, multiple-data (SIMD) computational architecture On-chip memory--5 Mbits on-chip RAM, 4 Mbits on-chip ROM to 450 MHz operating frequency Code compatible with all other members of the SHARC family The ADSP-2148x processors are available with unique audiocentric peripherals, such as the digital applications interface, serial ports, precision clock generators, S/PDIF transceiver, asynchronous sample rate converters, input data port, and more For complete ordering information, see Ordering Guide on Page 66 Qualified for automotive applications

Instruction Cache 5 Stage Sequencer Core Timer Block 0 RAM/ROM Block 1 RAM/ROM Block 2 RAM Block 3 RAM

SPEP BUS CORE FLAGS/ PWM3-1 PCG C-D TIMER 1-0 TWI SPI/B UART S/PDIF PCG Tx/Rx A-D ASRC PDAP/ SPORT IDP 3-0 7-0 WDT CORE PWM FLAGS 3-0 AMI SDRAM CTL

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

General Description................................................. 3 Family Core Architecture........................................ 4 Family Peripheral Architecture................................ 7 I/O Processor Features......................................... 10 System Design.................................................... 11 Development Tools............................................. 12 Additional Information........................................ 13 Related Signal Chains.......................................... 13 Pin Function Descriptions....................................... 14 Specifications........................................................ 18 Operating Conditions.......................................... 18 Electrical Characteristics....................................... 19 Absolute Maximum Ratings.................................. 21 ESD Sensitivity................................................... 21 Maximum Power Dissipation................................. 21 Package Information............................................ 21 Timing Specifications........................................... 22 Output Drive Currents......................................... 55 Test Conditions.................................................. 55 Capacitive Loading.............................................. 55 Thermal Characteristics........................................ 56 100-LQFP_EP Lead Assignment................................ 58 176-Lead LQFP_EP Lead Assignment......................... 60 Outline Dimensions................................................ 64 Surface-Mount Design.......................................... 65 Automotive Products........................................... 66 Ordering Guide.................................................. 66

C to Rev. D Changes to AMI Read.............................................. 33 Updated Outline Dimensions.................................... 64 Changes to Automotive Products................................ 66 Changes to Ordering Guide....................................... 66

The ADSP-2148x SHARC® processors are members of the SIMD SHARC family of DSPs that feature Analog Devices' Super Harvard Architecture. The processors are source code compatible with the ADSP-2146x, ADSP-2147x and ADSP-2116x DSPs, as well as with first generation ADSP-2106x SHARC processors in SISD (single-instruction, single-data) mode. The ADSP-2148x processors are 32-bit/40-bit floating point processors optimized for high performance audio applications with large on-chip SRAM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital applications interface (DAI). Table 1 shows performance benchmarks for the ADSP-2148x processors. Table 2 shows the features of the individual product offerings.

Benchmark Algorithm 1024 Point Complex FFT (Radix 4, with Reversal) FIR Filter (per Tap)1 IIR Filter (per Biquad)1 Matrix Multiply (Pipelined) Divide (y/×) Inverse Square Root Speed (at 400 MHz) 11.25 ns Speed (at 450 MHz) 10.0 ns

Feature Maximum Instruction Rate RAM ROM Audio Decoders in ROM2 Pulse-Width Modulation DTCP Hardware Accelerator External Port Interface (SDRAM, AMI)3 Serial Ports Direct DMA from SPORTs to External Port (External Memory) FIR, IIR, FFT Accelerator Watchdog Timer MediaLB Interface IDP/PDAP UART DAI (SRU)/DPI (SRU2) S/PDIF Transceiver SPI TWI SRC Performance4 Thermal Diode VISA Support Package3

4 Mbits Yes 4 Units (3 Units on 100-Lead Packages) Contact Analog Devices AMI Only Yes (16-bit) 8 Yes (176-Lead Package Only) Automotive Models Only Yes 1 Yes ­128 dB Yes 176-Lead LQFP EPAD

See Ordering Guide on Page 66. ROM is factory programmed with latest multichannel audio decoding and post-processing algorithms from Dolby® Labs and DTS®. Decoder/post-processor algorithm combination support varies depending upon the chip version and the system configurations. Please visit www.analog.com for complete information. 3 The 100-lead packages do not contain an external port. The SDRAM controller pins must be disabled when using this package. For more information, see Pin Function Descriptions on Page 14. The ADSP-21486 processor in the 176-lead package also does not contain a SDRAM controller. For more information, see 176-Lead LQFP_EP Lead Assignment on page 60. 4 Some models have ­140 dB performance. For more information, see Ordering Guide on page 66. 5 Only available to 400 MHz. See Ordering Guide on Page 66 for details.


 

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