Details, datasheet, quote on part number: TPS51206DSQR
PartTPS51206DSQR
CategorySemiconductors => Power Management => DDR Memory Power Solutions
Part familyTPS51206 2A Peak Sink/Source DDR Termination Regulator with VTTREF Buffered Reference for DDR2/3/3L/4
TitleIC REG SINK/SOURCE DDR 10SON
Description2A Peak Sink/Source DDR Termination Regulator with VTTREF Buffered Reference for DDR2/3/3L/4 10-WSON -40 to 85
CompanyTexas Instruments Inc.
StatusACTIVE
ROHSY
SampleYes
DatasheetDownload TPS51206DSQR datasheet
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Specifications 
Approx. Price (US$)0.25 | 1ku
Iq(Typ)(mA)0.17
Operating Temperature Range(C)-40 to 85
Control ModeN/A
RatingCatalog
Regulator TypeLinear Regulator
Vout VTT(Min)(V)0.6
Vin Bias(Max)(V)6.5
Vin(Max)(V)3.5
Package GroupWSON
Vin(Min)(V)1
Vin Bias(Min)(V)3.1
DDR Memory TypeDDR,DDR2,DDR3,DDR3L,DDR4,LPDDR2,LPDDR3
FeaturesS3/S5 Support
OutputVREF,VTT
Iout VTT(Max)(A)2
  Mecanical Data
Pin nbPackage typeInd stdJEDEC codePackage qtyCarrierDevice markWidth (mm)Length (mm)Thick (mm)Pitch (mm)
10DSQWSONS-PDSO-N3000LARGE T&R1206 22.75.4
Evaluation Kits
TPS51206EVM-745: 2-A Peak Sink/Source DDR Termination Regulator With VTTREF Buffered Reference
Spice Model
TPS51206 TINA-TI Transient Spice Model - ZIP (11/30/2011)
TPS51206 PSpice Transient Model - ZIP (08/10/2011)

Others parts numbering
TPS51200DRCR: IC CONV DDR DDR2 DDR3 10SON
TPS51200QDRCRQ1
TPS51206DSQT
TPS51200DRCT: IC SINK/SOURCE DDR REG 10-SON
TPS51200DRCTG4: IC CONV DDR DDR2 DDR3 10SON
TPS5120DBT: IC REG CTRLR BUCK 30TSSOP
TPS5120DBTR
TPS5120QDBTRQ1G4
TPS51200MDRCTEP: IC REG DDR 10VSON
TPS5120QDBTREP: IC REG CTRLR BUCK 30TSSOP
TPS5120MDBTREP
TPS51200DRCRG4: IC CONV DDR DDR2 DDR3 10SON
TPS51206EVM-745: EVAL MODULE FOR TPS51206-745
TPS51200EVM: EVALUATION MODULE FOR TPS51200

 

Features, Applications

2-A Peak Sink/Source DDR Termination Regulator with VTTREF Buffered Reference For DDR2, DDR3 and DDR3L

FEATURES

Supply Input Voltage: Supports 3.3-V Rail and 5-V Rail VLDOIN Input Voltage Range: 3.5 V VTT Termination Regulator Output Voltage Range: 2-A Peak Sink and Source Current Requires Only 10- F MLCC Output Capacitor 20 mV Accuracy VTTREF Buffered Reference 1% Accuracy 10-mA Sink/Source Current Supports High-Z in S3 and Soft-Stop in S4/S5 with S3/S5 Inputs Over Temperature Protection x 2mm SON(DSQ) Package

APPLICATIONS
DESCRIPTION

The is a sink/source double date rate (DDR) termination regulator with VTTREF buffered reference output. It is specifically designed for low input voltage, low cost, low external component count systems where space is a key consideration. The TPS51206 maintains fast transient response and only requires 10-F of ceramic output capacitance. The TPS51206 supports a remote sensing function and all power requirements for DDR2, DDR3 and Low-Power DDR3 (DDR3L) VTT bus. The VTT current capability is 2A peak. The TPS51206 supports all of the DDR power states, putting VTT to High-Z in S3 state (suspend to RAM) and discharging VTT and VTTREF in S4/S5 state (suspend to disk). The TPS51206 is available 10-pin, 2x2, SON (DSQ) PowerPADTM package and specified from to 85C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

(1) (2) PACKAGE Plastic SON ORDERABLE DEVICE NUMBER TPS51206DSQR TPS51206DSQT PINS 10 OUTPUT SUPPLY Tape and Reel QUANTITY 3000 250

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the TI website at www.ti.com. Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package

VALUE MIN VDD, S3, S5 Input voltage range (2) Output voltage range (2) Electrostatic discharge Junction temperature, TJ Operating free-air temperature, (2) 55 VLDOIN, VTTSNS, VDDQSNS PGND VTT, VTTREF HBM QSS 009-105 (JESD22-A114A) CDM QSS 009-147 (JESD22-C101B.01) MAX C V UNIT V

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted.

Operating free-air temperature, TA (1) All voltage values are with respect to the network ground terminal unless otherwise noted.

TPS51206 THERMAL METRIC JA JCtop JT JB JCbot (1) 2 Junction-to-ambient thermal resistance Junction-to-case (top) thermal resistance Junction-to-board thermal resistance Junction-to-top characterization parameter Junction-to-board characterization parameter Junction-to-case (bottom) thermal resistance

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Product Folder Link(s): TPS51206

over operating free-air temperature range, VVDD=5 V, VLDOIN is connected to VDDQSNS, VS3=VS5=5 V (unless otherwise noted)

PARAMETER SUPPLY CURRENT IVDD(S0) IVDD(S3) IVDDSDN IVLDOIN(S0) IVLDOIN(s3) IVLDOINSDN VVTTREF VVTTREFTOL IVTTREFSRC IVTTREFSNK IVTTREFDIS VTT OUTPUT VVTT Output voltage |IVTT| 10 mA, 1.4 V VVDDQSNS 1.8 V |IVTT|< 1.4 V VVDDQSNS V (1) VVTTTOL Output voltage tolerance to VVDDQSNS/2 |IVTT|< 1.4 V VVDDQSNS V (1) |IVTT| 10 mA, 1.2 V VVDDQSNS 1.4 V |IVTT|< 1.2 V VVDDQSNS V (1) |IVTT|< 1.2 V VVDDQSNS V (1) IVTTOCLSRC IVTTOCLSNK IVTTLK IVTTSNSBIAS IVTTSNSLK IVTTDIS VDDQ INPUT IVDDQSNS VDDQSNS input current VVDDQSNS 1.8 V Wake up Hysteresis 30 A Source current limit Sink current limit Leakage current VTTSNS input bias current VTTSNS leakage current VTT Discharge current VVDDQSNS 1.8 V, VVTT = VVTTSNS 0.7 V VVDDQSNS 1.8 V, VVTT = VVTTSNS 5 V, VVTT = VVTTREF 5 V, VVTTSNS = VVTTREF 5 V, VVTTSNS = VVTTREF VS5 = VVDDQSNS 0 V, VVTT mV V VDD supply current, in S0 VDD supply current, in S3 VDD shutdown current, in S4/S5 VLDOIN supply current, in S0 VLDOIN supply current, in S3 VLDOIN shutdown current, 25C, No load, 5 V, VVDDQSNS 25C, No load, 5 V, VVDDQSNS 25C, No load, 0 V, VVDDQSNS 25C, No load, 5 V, VLDION 25C, No load, 5 V, VLDION 25C, No load, 0 V, VLDION V VVDDQSNS/2 |IVTTREF|< 10 mA, 1.5 V VVDDQSNS 1.8 V |IVTTREF|< 10 mA, 1.2 V VVDDQSNS 1.5 V VVDDQSNS 1.8 V, VVTTREF 0 V VVDDQSNS 0 V, VVTTREF = 0V, VVTTREF 0.5V mA TEST CONDITION MIN TYP MAX UNIT

VTTREF OUTPUT Output voltage Output voltage tolerance to VVDDQSNS Source current Sink current VTTREF Discharge current V

UVLO/LOGIC THRESHOLD VVDDUV VLL VLH VLHYST ILHLK VDD UVLO threshold voltage S3/S5 low-level voltage S3/S5 high-level voltage S3/S5 hysteresis voltage S3/S5 input leak current Shutdown temperature (1) Hysteresis

OVER-TEMPERATURE PROTECTION TOTP Over temperature protection 10 C
Submit Documentation Feedback Product Folder Link(s): TPS51206

 

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