Details, datasheet, quote on part number: R7FS5D57C3A01CFP#AA0
TitleARM Microcontrollers - MCU SYNERGY MCU S5D5 384k 100LQFP
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Features, Applications

All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp. website (

Leading performance 120-MHz ARM® Cortex®-M4 core, to 1-MB code flash memory, 384-KB SRAM, Capacitive Touch Sensing Unit, Ethernet MAC Controller, USB 2.0 Full-Speed, SDHI, Quad SPI, security and safety features, and advanced analog.

ARM Cortex-M4 Core with Floating Point Unit (FPU)

ARMv7E-M architecture with DSP instruction set Maximum operating frequency: 120 MHz Support for 4-GB address space On-chip debugging system: JTAG, SWD, and ETM Boundary scan and ARM Memory Protection Unit (MPU) to 1-MB code flash memory (40 MHz zero wait states) 32-KB data flash memory (up to 100,000 erase/write cycles) to 384-KB SRAM Flash Cache (FCACHE) Memory Protection Units (MPU) Memory Mirror Function (MMF) 128-bit unique ID

Low power modes Realtime Clock (RTC) with calendar and VBATT support Event Link Controller (ELC) DMA Controller (DMAC) × 8 Data Transfer Controller (DTC) Key Interrupt Function (KINT) Power-on reset Low Voltage Detection (LVD) with voltage settings 3DES/ARC4 SHA1/SHA224/SHA256 GHASH RSA/DSA True Random Number Generator (TRNG)

Ethernet MAC Controller (ETHERC) Ethernet DMA Controller (EDMAC) USB 2.0 Full-Speed Module (USBFS) - On-chip transceiver Serial Communications Interface (SCI) with FIFO × 10 Serial Peripheral Interface (SPI) 2 I2C bus interface (IIC) × 3 CAN module (CAN) × 2 Serial Sound Interface Enhanced (SSIE) SD/MMC Host Interface (SDHI) × 2 Quad Serial Peripheral Interface (QSPI) IrDA interface Sampling Rate Converter (SRC) External address space or 16-bit bus space is selectable per area - SDRAM support 12-bit A/D Converter (ADC12) with 3 sample-and-hold circuits each 2 12-bit D/A Converter × 2 High-Speed Analog Comparator (ACMPHS) × 6 Temperature Sensor (TSN) General PWM Timer 32-Bit Enhanced High Resolution × 4 General PWM Timer 32-Bit Enhanced × 4 General PWM Timer × 6 Asynchronous General-Purpose Timer (AGT) × 2 Watchdog Timer (WDT) ECC in SRAM parity error check Flash area protection ADC self-diagnosis function Clock Frequency Accuracy Measurement Circuit (CAC) Cyclic Redundancy Check (CRC) calculator Data Operation Circuit (DOC) Port Output Enable for GPT (POEG) Independent Watchdog Timer (IWDT) GPIO readback level detection Register write protection Main oscillator stop detection Illegal memory access

Capacitive Touch Sensing Unit (CTSU) Parallel Data Capture Unit (PDC) Main clock oscillator (MOSC) to 24 MHz) Sub-clock oscillator (SOSC) (32.768 kHz) High-speed on-chip oscillator (HOCO) (16/18/20 MHz) Middle-speed on-chip oscillator (MOCO) (8 MHz) Low-speed on-chip oscillator (LOCO) (32.768 kHz) Independent Watchdog Timer OCO (15 kHz) Clock trim function for HOCO/MOCO/LOCO Clock out support

to 110 input/output pins to 1 CMOS input to 109 CMOS input/output to 21 input/output 5 V tolerant to 18 high current (20 mA) VCC: 3.6 V

The MCU integrates multiple series of software- and pin-compatible ARM®-based 32-bit MCUs that share a common set of Renesas peripherals to facilitate design scalability and efficient platform-based product development. The MCU provides a high-performance ARM Cortex®-M4 core running to 120 MHz with the following features: to 1-MB code flash memory 384-KB SRAM Capacitive Touch Sensing Unit (CTSU) Ethernet MAC Controller (ETHERC), USBFS, SD/MMC Host Interface Quad Serial Peripheral Interface (QSPI) Security and safety features 12-Bit A/D Converter (ADC12) 12-Bit D/A Converter (DAC12) Analog peripherals.


Functional description Maximum operating frequency: to 120 MHz ARM Cortex-M4 core: - Revision: - ARMv7E-M architecture profile - Single precision floating-point unit compliant with the ANSI/IEEE Std 754-2008. ARM Memory Protection Unit (MPU): - ARMv7 Protected Memory System Architecture - 8 protect regions. SysTick timer: - Driven by LOCO clock.

Functional description Maximum MB of code flash memory. See section 53, Flash Memory in User's Manual. KB of data flash memory. See section 53, Flash Memory in User's Manual. The MMF can be configured to mirror the target application image load address in code flash memory to the application image link address in the 23-bit unused memory space (memory mirror space addresses). Your application code is developed and linked to run from this MMF destination address. The application code does not need to know the load location where it is stored in code flash memory. See section 5, Memory Mirror Function in User's Manual. The option-setting memory determines the state of the MCU after a reset. See section 7, Option-Setting Memory. On-chip high-speed SRAM providing either parity-bit or Error Correction Code (ECC). The first SRAM0 is subject to ECC. Parity check is performed for other areas. See section 51, SRAM in User's Manual. On-chip SRAM that can retain data in Deep Software Standby mode. See section 52, Standby SRAM in User's Manual.

Code flash memory Data flash memory Memory Mirror Function (MMF)


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