Details, datasheet, quote on part number: AD9543/PCBZ
PartAD9543/PCBZ
Category
TitleEVALUATION BOARD AD9543
Description

ADI’s AD9543 is a four input and ten clock output digital phase lock loop (PLL) that reduces timing jitter associated with the external references. The digitally controlled loop and holdover circuitry continuously generate a low jitter output signal, even when all reference inputs fail. The device’s dual DPLL synchronizes 2 kHz to 750 MHz physical layer clocks providing frequency translation with jitter cleaning of noisy references. The AD9543 is available in a 48-lead LFCSP (7 mm × 7 mm) package and operates over the -40°C to +85°C temperature range. This device complies with ITU-T G.8262 and Telcordia GR-253, and supports Telcordia GR-1244, ITU-T G.812, G.813, G.823, G.824, G.825, and G.8273.2. The AD9543 is ideal for base stations and carrier Ethernet.



CompanyAnalog Devices
DatasheetDownload AD9543/PCBZ datasheet
  

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AD9543BCPZ: BBU DERIVATIVE FOR AD9545

 

Features, Applications
FEATURES
Quad Input, 10-Output, Dual DPLL/IEEE 1588 Synchronizer and Jitter Cleaner AD9543
APPLICATIONS

PTP (IEEE 1588), and SyncE jitter cleanup and synchronization Optical transport networks (OTN), SDH, and macro and small cell base stations OTN mapping/demapping with jitter cleaning Small base station clocking, including baseband and radio Stratum 2, Stratum 3e, and Stratum 3 holdover, jitter cleanup, and phase transient control JESD204B support for analog-to-digital converter (ADC) and digital-to-analog converter (DAC) clocking Cable infrastructures Carrier Ethernet

Dual DPLL synchronizes 2 kHz to 750 MHz physical layer clocks providing frequency translation with jitter cleaning of noisy references Complies with ITU-T G.8262 and Telcordia GR-253 Supports Telcordia GR-1244, ITU-T G.824, G.825, and G.8273.2 Continuous frequency monitoring and reference validation for frequency deviation as low as 50 ppb Both DPLLs feature a 24-bit fractional divider with 24-bit programmable modulus Programmable digital loop filter bandwidth: 1850 Hz Two independent, programmable auxiliary NCOs to 65,535 Hz, resolution Hz), suitable for IEEE 1588 Version 2 servo feedback in PTP applications Automatic and manual holdover and reference switchover, providing zero delay, hitless, or phase buildout operation Programmable priority-based reference switching with manual, automatic revertive, and automatic nonrevertive modes supported 5 pairs of clock output pins with each pair useable as differential LVDS/HCSL/CML as 2 single-ended outputs to 500 MHz) 2 differential or 4 single-ended input references Crosspoint mux interconnects reference inputs to PLLs Supports embedded (modulated) input/output clock signals Fast DPLL locking modes Provides internal capability to combine the low phase noise of a crystal resonator or crystal oscillator with the frequency stability and accuracy of a TCXO or OCXO External EEPROM support for autonomous initialization Single 1.8 V power supply operation with internal regulation Built in temperature monitor/alarm and temperature compensation for enhanced zero delay performance

The AD9543 supports existing and emerging ITU standards for the delivery of frequency, phase, and time of day over service provider packet networks. The 10 clock outputs of the AD9543 are synchronized to any one up to four input references. The digital phase-locked loops (DPLLs) reduce timing jitter associated with the external references. The digitally controlled loop and holdover circuitry continuously generate a low jitter output signal, even when all reference inputs fail. The AD9543 is available a 48-lead LFCSP 7 mm) package and operates over the to +85C temperature range. Note that throughout this data sheet, multifunction pins, such as SDO/M5, are referred to either by the entire pin name by a single function of the pin, for example, M5, when only that function is relevant.

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AD9543 Material Declaration PCN-PDN Information Quality And Reliability Symbols and Footprints

Data Sheet AD9543: Quad Input, 10-Output, Dual DPLL/IEEE 1588 Synchronizer and Jitter Cleaner User Guides AD9543 Evaluation Board User Guide UG-1167: Register Map Reference Manual for the AD9543

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Features.............................................................................................. 1 Applications....................................................................................... 1 General Description......................................................................... 1 Revision History............................................................................... 3 Functional Block Diagram.............................................................. 4 Specifications..................................................................................... 5 Supply Voltage............................................................................... 5 Supply Current.............................................................................. 5 Power Dissipation......................................................................... 5 System Clock Inputs, XOA and XOB......................................... 6 Reference Inputs........................................................................... 7 Reference Monitors...................................................................... 8 DPLL Phase Characteristics........................................................ 9 Distribution Clock Outputs........................................................ 9 Time Duration of Digital Functions........................................ 10 Digital PLL (DPLL0, DPLL1) Specifications.......................... 11 Digital PLL Lock Detection Specifications............................. 11 Holdover Specifications............................................................. 12 Analog PLL (APLL0, APLL1) Specifications.......................... 12 Output Channel Divider Specifications.................................. 12 Auxiliary Circuit Specifications................................................ 13 System Clock Compensation Specifications........................... 13 Temperature Sensor Specifications.......................................... 13 Serial Port Specifications........................................................... 14 Logic Input Specifications (RESETB, M6).................. 16 Logic Output Specifications M6)................................ 16 Jitter Generation (Random Jitter)............................................ 17 Phase Noise................................................................................. 18 Absolute Maximum Ratings.......................................................... 21 Thermal Resistance.................................................................... 21 ESD Caution................................................................................ 21 Pin Configuration and Function Descriptions........................... 22 Typical Performance Characteristics........................................... 25 Terminology.................................................................................... 29 Theory of Operation...................................................................... 30 Overview...................................................................................... 30 Reference Input Physical Connections.................................... 30 Input/Output Termination Recommendations.......................... 31 System Clock Inputs................................................................... 31 Reference Clock Inputs.............................................................. 31

Clock Outputs............................................................................. 32 System Clock PLL........................................................................... 33 System Clock Input Frequency Declaration........................... 33 System Clock Source.................................................................. 33 2 Frequency Multiplier............................................................ 33 Prescale Divider.......................................................................... 34 Feedback Divider........................................................................ 34 System Clock PLL Output Frequency..................................... 34 System Clock PLL Lock Detector............................................. 34 System Clock Stability Timer.................................................... 34 System Clock Input Termination Recommendations........... 34 Digital PLL (DPLL)........................................................................ 35 Overview..................................................................................... 35 DPLL Phase/Frequency Lock Detectors................................. 35 DPLL Loop Controller............................................................... 35 Applications Information.............................................................. 36 Optical Networking Line Card................................................. 36 Small Cell Base Station.............................................................. 37 IEEE 1588 Servo......................................................................... 38 Initialization Sequence................................................................... 39 Status and Control Pins................................................................. 42 Multifunction Pins at Reset/Power-Up................................... 43 Status Functionality.................................................................... 43 Control Functionality................................................................ 44 Interrupt Request (IRQ)................................................................ 48 IRQ Monitor............................................................................... 48 IRQ Mask..................................................................................... 48 IRQ Clear..................................................................................... 48 Watchdog Timer............................................................................. 50 Lock Detectors................................................................................ 51 DPLL Lock Detectors................................................................ 51 Phase Step Detector........................................................................ 53 Phase Step Limit......................................................................... 53 Skew Adjustment........................................................................ 54 EEPROM Usage.............................................................................. 55 Overview..................................................................................... 55 EEPROM Controller General Operation................................ 55 EEPROM Instruction Set.......................................................... 56 Multidevice Support................................................................... 58 Serial Control Port......................................................................... 60


 

Some Part number from the same manufacture Analog Devices
AD9543BCPZ

ADI’s AD9543 is a four input and ten clock output digital phase lock loop (PLL) that reduces timing jitter associated with the external references. The digitally controlled loop and holdover circuitry

 
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