|Category||Communication => Wireless => Bluetooth|
|Description||Bluetooth Single Chip<<<>>>the STLC2500 is a Single Chip ROM-based Bluetooth<<<>>>solution Implemented in 0.13 M Ultra Low<<<>>>power, Low Leakage CMOS Technology For Applications<<<>>>requiring Integration up to Hci Level. Patch<<<>>>ram is Available Enabling Multiple Patches/upgrades.<<<>>>the STLC2500's Main Interfaces Are Uart For<<<>>>hci Transport, PCM For Voice And Gpios For Control<<<>>>purposes. The Radio is Designed For The Single<<<>>>chip Requirement And For Drastic Power Consumption<<<>>>reduction.|
|Company||ST Microelectronics, Inc.|
|Datasheet||Download STLC2500 datasheet
FEATURES BluetoothTM specification compliance: V1.1 and V1.2 Ericsson Licensing Technology Baseband Core (EBC) Point-to-point, point-to-multi-point (up to 7 slaves) and scatternet capability Asynchronous Connection Oriented (ACL) logical transport link Synchronous Connection Oriented (SCO) link: 2 simultaneous SCO channels Support Pitch-Period Error Concealment (PPEC) Improves speech quality in the vicinity of interference Improves coexistence with WLAN Works at receiver, no Bluetooth implication Adaptive Frequency Hopping (AFH): hopping kernel, channel assessment as Master and as Slave Faster Connection: Interlaced scan for Page and Inquiry scan, first FHS without random back off, RSSI used to limit range Extended SCO (eSCO) links HW support for packet types ACL: 3, 5 and 5 SCO: HV1, 3 and DV eSCO: EV3, 5 Clock support System clock input (digital or sine wave) or 38.4 MHz LPO clock input or 32.768 kHz ARM7TDMI CPU 32-bit Core AMBA (AHB-APB) bus configuration Patch RAM capability Memory organization On chip RAM, including provision for patches On chip ROM, preloaded with up to HCI Communication interfaces Fast UART PCM interface 4 programmable GPIOs External interrupts possible through the GPIOs Fast master I2C interface Efficient support for WLAN coexistence in collocated scenario Ciphering support to 128 bits key Software support Lower level stack (up to HCI) HCI Transport Layer: H4 (including propri-
etary extensions) HCI proprietary commands (e.g. peripherals control) Single HCI command for patch/upgrade download Single power supply with internal regulators for core voltage generation Supports to 2.85 Volts IO systems Total number of external components limited 7 (6 decoupling capacitors and 1 filter) thanks to: Fully integrated synthesizer (VCO and loop filter) Integrated antenna switch Low IF receiver Auto calibration (VCO, Filters) No need for calibration of the RF part Timer and watchdog Power class 2 compatible Ultra low power architecture with 3 different low power levels: Sleep Mode Deep Sleep Mode Complete Power Down Mode Software Initiated Low Power Mode Dual Wake-up mechanism: initiated either by the Host or by the Bluetooth device Standard TFBGA-84 pins package
2 DESCRIPTION The is a single chip ROM-based Bluetooth solution implemented 0.13 m ultra low power, low leakage CMOS technology for applications requiring integration up to HCI level. Patch RAM is available enabling multiple patches/upgrades. The STLC2500's main interfaces are UART for HCI transport, PCM for voice and GPIOs for control purposes. The Radio is designed for the single chip requirement and for drastic power consumption reduction.
This is preliminary information on a new product now in development. Details are subject to change without notice.
3 QUICK REFERENCE DATA VDD_IO_x means VDD_IO_A, VDD_IO_B. (See also table 13 subsection Power supply.) 3.1 Absolute Maximum Ratings The Absolute Maximum Rating (AMR) corresponds to the maximum value that can be applied without leading to instantaneous or very short-term unrecoverable hard failure (destructive breakdown). Table 2. Absolute Maximum Ratings
Symbol VDD_HV VDD_IO_x Vssdiff Vin Tstg Tlead Supply voltage I/O Maximum voltage difference between different types of VSS pins Input voltage of any digital pin Storage temperature Lead temperature <10s Parameter Regulator input supply voltage Min. Vss - 0.3 Vss 0.3 -0.3 Vss 0.3 -65 Max. Unit °C
3.2 Operating Ranges Operating ranges define the limits for functional operation and parametric characteristics of the device. Functionality outside these limits is not implied. Table 3. Operating ranges
Symbol Tamb VDD_HV VDD_IO_A VDD_IO_B Parameter Operating ambient temperature Regulator input supply voltage Supply voltage for I/O Supply voltage for I/O Min. Typ. Max. UnitThe chip will be characterized from 2.62 [V] to 2.9 [V]. The chip will be characterized to 2.9 [V].
3.3 I/O specifications The I/Os comply with the EIA/JEDEC standard JESD8-B. Table 4. DC Input specification (all digital I/Os except system clock)
Symbol VIL VIH Vhyst Parameter Low Level input voltage High Level input voltage Schmitt trigger hysteresis 0.65 * VDD_IO_x 0.5 0.6 Min. Typ. Max. 0.35 * VDD_IO_x Unit V
Symbol VOL VOH Parameter Low Level output voltage High Level output voltage Condition X mA VDD_IO_x - 0.15 Min. Typ. Max. 0.15 Unit V
Note: X is the source/sink current under worst-case conditions according to the drive capabilities (see section 5)
3.4 Clock specifications The STLC2500 supports, on the same input pin, the system clock both as a sine wave clock and as a digital clock (see table 15 for selection). The system clock section is powered by VDD_CLD (G08 and H09). The voltage range for VDD_CLD is the same as for VDD_IO_A. Table 6. System clock supported frequenciesSymbol FIN Parameter Clock input frequency list Values Unit MHz
Symbol FINTOL Parameter Tolerance on input frequency Min. -20 Typ. Max. 20 Unit ppm
Table 8. System clock, sine wave specifications
Symbol VPP NH ZINRe Parameter Peak to peak voltage range Total harmonic content of input signal Real part of parallel input impedance at pin 30 60 Min. 0.2 Typ. 0.5 Max. -25 90 Unit V dBc KTable 9. System clock, digital clock DC specifications
Symbol VIL VIH Parameter Low Level input voltage High Level input voltage 0.85 * VDD_IO_A Min. Typ. Max. 0.22 * VDD_IO_A Unit VTable 10. System clock, digital clock AC specifications
Symbol TRISE TFALL DCYCLE Parameter 10%-90% rise time 90%-10% fall time Duty Cycle 45 Min. Typ. 1,5 50 Max. 6 55 Unit ns %
Table 11. Low Power clock specifications The low power clock pin is powered by connecting VDD_IO_B to the wanted supply.Symbol Duty Cycle Accuracy Parameter Min. 30 Typ. Max. 70 ±250 Unit % ppm
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