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Part: 09E1E40

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1300 nm ESCON® Parallel Transceiver
Preliminary Data Sheet
FEATURES · Complies with ESCON and SBCON standards · Fully compatible with parallel transceiver V23806-A6-X1 · Transceiver includes clock recovery module, P-S /S-P and ESCON/SBCON receptacle · Optional 8B/10B coder/decoder function (E40 only) · SMT component for easy mounting on surface mount PC boards · Transceiver mates keyed ESCON/ SBCON connector · Data rates for ESCON/SBCON applications from 100 to 200 MBaud · Data rates for individual applications from 100 to 300 MBaud · Transmission distance of 3 km and more · Single power supply of 3.0 V to 5.5 V (E40 only) · Extremely low power consumption <2 W at 3.3 V (E40 only) · All inputs and outputs TTL compatible · Excellent EMI performance · System optimized for 62.5 and 50 µm graded index fiber · 0.7" spacing between optical interface of transmitter and receiver · Low profile for high slot density APPLICATIONS · ESCON architecture · High speed computer links · Local area networks · High definition/digital television · Switching systems · Control systems · FC transceiver version with SC duplex shell planned Dimensions in inches (mm)
A .096 (2.46) .048 (11.9) .145 (3.7) optical reference plane .088 (2.24) 1.762(44.83) (51x) .012 (0.3) 0.6 M A M

V23809-E1-E30 8B/10BV23809-E1-E40

5.08 .090 (2.31) min 1.2 (PCB-thickness) 30.48 (12")

0.05 M A M (17­1)x1.27=20.32 .448(11.4)

mounting screw M2.5

11.9

s

V23809­E1­E4 PARALLEL ESCON TRX

1.262 1.379 (32.1) 35.4 (35.1) (1.4"max)

x96050001x MADE IN GERMANY

1.254 (31.9)

.890(15) 3.341(85)

1.018(25.9)

Maximum Ratings (Absolute maximum stress) Exceeding any one of these values may destroy the device immediately. However, the electro-optical characteristics described in the following tables are only valid for use under the recommended operating conditions. Power Dissipation (PD)..... 2 W Supply voltage (VCC­VEE) ........... ­0.5 V to7 V Maximum Inqut Voltage (VIN) ........ VEE to VCC Operating Case Temperature (Tcase) ......... ­25 to 85°C Humidity/Temperature Test Condition (RH) .......... 85/85 %/°C Lifetest Condition (Tamb/life).....115/1000°C/h Soldering Conditions Temp/Time (Tsold) ...... 260/10°C/s ESD Resistance (all pins to VEE, Human Body) (ESD) ..........1.5 kV Output Current (lo)........ 50 mA ESCON® is a registered trademark of IBM.

1

DESCRIPTION The Siemens ESCON/SBCON optical devices, along with the ESCON/SBCON optical duplex connector, are best suited for high speed fiber optic duplex transmission systems operating at a wavelength of 1300 nm. The system is fully compatible with the IBM ESCON standard and the upcoming SBCON of ANSI. It includes a transmitter and a receiver as well as the clock recovery function and the serial/parallel interfaces. In addition, an 8 B/10 B coder-decoder function can be used optionally. The ESCON Parallel Transceiver is designed for data rates of up to 300 MBaud. A non-dissipative plastic receptacle matches the ESCON duplex connector. The inputs/outputs are TTL compatible and the unit operates on a single power supply from 3.0 to 5.5 V. The optical interface of transmitter and receiver have standard 0.7" spacing. Receptacle and connector have been keyed in order to prevent reverse insertion of the connector into the receptacle. After proper insertion the connector is securely held by a snap-in lock mechanism. The transmitter converts parallel electrical TTL input signals into an optical serial signal at data rates of between 100 and 300 MBaud. The receiver performs clock recovery on the incoming data stream and converts data to a parallel output. New Built-in Functions (E40 only) The ESCON Parallel Transceiver 8B/10B contains an encoder/decoder unit, a serial/parallel converter part, a synthesizer/clock recovery PLL section, and a TTL input and a PECL output interface, as well as the serial electro-optical converting function. The data from the parallel TTL input interface are converted to a serial bitstream feeding an LED driver. The differential receiver signal is converted to parallel data words at the TTL output. This transceiver meets the requirements for the IBM ESCON® standard. Figure 1. PSOL module overview
CONTROL LEDdriver PSOL MAIN IC Preamplifier O E Optical input E O Optical output

b) PSOL mode: conversion of 8 bit electrical data words to a serial optical bitstream using an 8B/10B encoder for optical data transmission and conversion of a serial bitstream to 10 bit-wide electrical data words using a 10B/8B decoder. Switching between the two modes is done by applying Vcc or GND to the FSOL/PSOL pins respectively. Figure 2. Functionality: PSOL main IC in FSOL mode

Figure 3. Functionality: PSOL main IC in PSOL mode

Recommended Operating Conditions
Parameter Operating Ambient Temperature Power Supply Voltage Supply Current 3.3 V Supply Current 5 V Data Input High Voltage Data Input Low Voltage Input Data Rise/Fall, 10­90% Output Current High Output Current Low VIH VIL t ,t lo lCC2
RF

Sym. TC VCC­VEE ICC

Min 0 3

Max 70 5.5 300 400

Units

°C
V mA

2 Vee 0.4

VCC 0.8 1.3 ­0.4 4

V

ns mA

TBCLK din a..j DOUT a..j RBCLK

Transmitter Electro-Optical Characteristics (Values in parentheses are for 300 MBd)
Transmitter Data Rate Supply Current 3.3 V(1) Supply Current 5 V(1) Launched Power (Ave.) BOL into 62.5µm Fiber (2, 3, 4) Launched Power (Ave.) EOL into 62.5µm Fiber (2, 3. 4. 7) Po ­21
(­22)

Sym. DR lCC

Min. Typ. 100

Max. Units 200
(320)

MBaud mA

ESCON Parallel 8B/10B Module

200 300 ­16.5 ­14

The transceiver can be operated in two modes: a) FSOL mode: conversion of 10 bit electrical data words to a serial bitstream and conversion of a serial bitstream to 10 bit-wide electrical data words. In this mode the transceiver can be used as a plug-in replacement for the Parallel Transceiver V23806-A6-X1.

dBm

­22
(­23)

2

V23809-E1-E30/E40, 1300 nm ESCON® Parallel Transceiver 8B/10B

Transmitter Center Wavelength(5, 6) Spectral Width (FWHM)(6) Temperature Coefficient, Optical Optput Power Output Rise/Fall Time, 20­80%(6) Deterministic Jitter(8) Random Jitter(9) Extinction Ratio (dynamic)(10)

Sym. lC TCp tR, tF Jd Jr ER

Min. 1285

Typ.

Max. Units 1355 nm 160 0.03 dB/°C ns

Receiver Signal Detect Hysteresis Signal Detect Reaction Time

Sym. PSDA­ PSDD SDrea c

Min. 0.5 3

Typ. 1.5

Max. 3 500 0.19 0.09

Units dB µs % of Unit Intervals

1 0.6

1.7
(2)

Max. Deterministic Jd Jitter Optical Input(7, 9) Max. Random Jitter Jr RMS Optical Input(8, 9)

0.8 0.06

­16

­13

dB

Notes 1. Transmitter operating at 200 MBaud and 50% duty cycle. 2. Measured at the end of 1 meter fiber, cladding modes removed at a data rate of between 50 and 200 MBaud, 50% duty cycle. 3. Po [dBm]=10 log (Po/1 mW) 4. Po (BOL) >­20dBm and Po (EOL) >­21.5 dBm at Tcase=60°C. 5. Measured at Tcase=60°C 6. Full width, half magnitude of peak wavelength: special relationship between c, d, tr/tf according to FC-PH Rev 4.3 Paragraph 6.3.2. and Fig.26. Spectral width must be considered. 7. Over 105 hours lifetime at Tamb=35°C 8. Deterministic Jitter, measured at 200 MBaud with Jitter Test Pattern shown in Figure 5. In the Test Pattern are five positive and five negative transitions. Measure the time of the 50% crossing of all 10 transitions. The time of each crossing is then compared to the mean expected time of the crossing. The DJ is the range of the timing variations. 9. RMS value measured with 1010 pattern at 200 Mbaud. Peak-topeak value is determined as RMS multiplied by 14 for BER 1E-12. 10. Extinction ratio is the logarithmic measure of the optical power in the OFF state (POFF) to twice the average power (P0): ER=10 log [(2xP0)/POFF]; optical power measured in mW or ER=P0+3dB­POFF; optical power measured in dBm

Notes 1. For VCC­VEE (min, max). 50% duty cycle. 2. Measured at the end of 1 meter fiber, cladding modes removed at a data rate of between 50 and 200 MBaud, 50% duty cycle. 3. Po [dBm]=10 log (Po [mW]) 4. Measured at BER=1E-12, 200 MBaud transmission rate and 50% duty cycle 27-1 PRBS pattern; center wavelength between 1200nm and 1500 nm, fiber type 62.5/125 µm/0.29 NA or 50/125 µm/0.2 NA; input optical rise and fall times are 1.2 ns and 1.5 ns (20% - 80%) respectively. 5. Over 105 hours lifetime at Tamb=35°C 6. Indicates the presence or absence of optical power at the receiver input. Signal detect at logic "high" when asserted. All powers are average power levels. Pattern 27-1 at 200 MBaud. 7. Deterministic Jitter measured at 200 MBaud with Jitter Test Pattern shown in Figure 5. In the test pattern are five positive and five negative transitions. Measure the time of the 50% crossing of all 10 transitions. The time of each crossing is then compared to the mean expected time of the crossing. The DJ is the range of the timing variations. 8. To convert from specified RMS value to peak-to-peak value (at BER 1E-12) multiply value by 14. 9. Jitter at optical input. Jitter magnitudes above specified level may increase the bit error rate.

Transceiver Pin Description 10 Bit Interface: FSOL Mode In this mode the transceiver is compatible with the former version, V23806-A6-X1
Pin# 1, 6, 9, 26, 43, 45, 48, 51 2 3 4 Pin Name Vee Level/Logic Description Power Supply Ground attached to the case Preamplifier positive power supply TTL out TTL in Signal detected Control input for RX PLL Control of byte alignment operation Power Supply TTL out TTL out Bipolar IC positive power supply Data output parallel 10 channels Read byte clock Parity bit out Byte synchronization operation TTL out Parity bit error

Receiver Electro-Optical Characteristics (Values in parentheses are for 300 MBd)
Receiver Data Rate Supply Current (1) Sensitivity (Average Power)BOL(2, 3, 4) Sensitivity (Average Power) EOL(2, 3, 4, 5) Saturation (Average Power) Signal Detect Assert Level(6) Signal Detect Deassert Level(6) Signal Detect Hysteresis Signal Detect Reaction Time PSAT PSDA PSDD PSDA­ PSDD SDreac Sym. Dr lCC PIN ­32.5
(­29)

Min. 100

Typ.

Max. 200
(300)

Units MBaud mA dBm

Vcc PRE SIGDET LOCKREF SYNCEN VccFAST Dout a to j RBCLK PAROUT BSYNC PARERR

100 ­35.5 ­35

­32
(­ 28.5)

5 7,8 ­36,0 ­37.5 10 to 19 20 dB µs 21 22 23

­14 ­44.5 ­45 0.5 3 1.5

3 500

3

V23809-E1-E30/E40, 1300 nm ESCON® Parallel Transceiver 8B/10B

Pin# 24,25 27 28 29 30 31 32 33 to 42 44 46 47 49,50

Pin Name VccSLOW Loopsel a Loopsel b RESREC RESFF TBCLK PARIN Din j to a TESTCLK TESTMOD TXOFF Vcc DRI

Level/Logic Description Power Supply TTL in Logic positive power supply Test loop select

Pin# 27 28 29

Pin Name Loopsel a Loopsel b EPI ENPI TBCLK PARIN TCV

Level/ Logic TTL in

Description Test loop select

Enable parallel input Enable next parallel input Transmit byte clock Parity bit in Transmitter code violation Uncoded data input parallel 8 channels Transmitter special character flag Select Raw Mode/Coder Mode Enable built-in self test Transceiver off when logical high Power Supply LED driver positive power supply

Receiver reset Reset all flip-flops Transmit byte clock Parity bit in Data input parallel 10 channels Test clock. In test mode this clock is the bit clock If this signal is low TESTCLK is used Transceiver off when logical high Power Supply LED driver positive power supply

30 31 32 33

34 to 41 Din H to A 42 44 46 47 49, 50 TK RAW/COD BIST TXOFF Vcc DRI

Transceiver Pin Description 8 Bit interface: PSOL Mode (E40 only)
Pin# 1, 6, 26, 43, 45, 48, 51 2 3 4 5 7,8 9 10 Pin Name Vee Level/ Logic Power Supply Description

Figure 4. Signal detect threshold and hysteresis
­37.5 dBm to ­45 dBm ­44.5 dBm to ­36 dBm

Ground attached to the case

Asserted

Vcc PRE SIGDET R SYNCEN VccFAST PSOL1/ PSOL2 RK TTL in Power Supply TTL in TTL out TTL out

Preamplifier positive power supply Signal detected Read pulse for external FIFOs Control of byte alignment operation Positive power supply of the bipolar IC Mode select for PSOL Mode 1 or Mode 2 Receiver special character flag Decoded data output parallel 8 channels Receiver code violation Read byte clock Parity bit out Write pulse for external FIFOs Parity bit error Power Supply Logic positive power supply

Deasserted 0.5 dB 1.5 dB 3 dB

delta PSD

Figure 5. Jitter test pattern
0011111101011000001010

11 to 18 Dout A to H 19 20 21 22 23 24, 25 RCV RBCLK PAROUT W PARERR VccSLOW

4

V23809-E1-E30/E40, 1300 nm ESCON® Parallel Transceiver 8B/10B

Block diagram of the ESCON transceiver in PSOL mode (E40 only)
TXOFF RP Reset TBCLK RAW/CO ENN ENA DIN 0.9 PARI 60/40 PLL x 10 0 BitClk select 1 BitClk AND EN OPT O 10 Parity checker 8+2 BISTEN LOOPSELa 0 Y0 Testloop L1 select Y1 L1 Y2 1 Y3 10 DOUT 0.9 PAROU RBCLK L3 1 8+1 Parity BIST Generator pattern & Output Buffer 8+2 RDY 0 RDY BIST pattern comparator 8+1 TX BIST control 8+2 10B P SPC D 10 S 10 TX BIST control 8B 10B 10 D P S C PSC TXCLK TXDAT EOC E TESTCLK TESTMOD TXOFF

L2 TXDAT C1 Data Retime select data C0 D L2 PLL C0 Clock Retime select CLK C1 C 8B L1 C1 C0 PLL input select TXCLK 60/40 RXDAT Buffer E OEC O

LOOPSELb

SYNCEN BSYNC

SIGDET

APPLICATION NOTE Power Supply Filtering In most of the applications using ESCON 200 MBd Optical Transceivers, additional high speed circuits such as switching power supply, clock oscillator, or high speed multiplexer are present on the application board. These often create power supply noise at a high spectral bandwidth, caused by very fast transitions in today's chip technology. The Siemens ESCON Transceiver Family provides superior EMI performance regarding emission and immission of radiation and provides immunity against conductive noise. Some basic recommendations are given in this document to ensure proper functionality in the field. For proper operation the use of a multilayer board with ground and Vcc plane is strongly recommended. The Vcc plane should be slotted as shown in Figure 6 to avoid crosstalk between different circuitry inside the module. The metallized package is internally connected to the VEE-pins of the module. Nevertheless the package must be connected externally to ground for best shielding characteristics. Ground contact should be made with the ground rings shown in Figure 6. Because of high switching currents at VCCDRI, the use of an external 6.8 to 22 µF capacitor is recommended at VCCDRI. The observance of normal design rules for high speed digital systems is sufficient to ensure safe operation.

Figure 6. Slotting of VCC plane

Slots

VccBIP VccPRE VccCMOS VccDRI

VCC Plane

Note: Slots are non-copper areas inside the VCC plane to avoid cross-current flow

5

V23809-E1-E30/E40, 1300 nm ESCON® Parallel Transceiver 8B/10B




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