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Part: 24WC01-16
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CAT24WC01/02/04/08/16
CAT24WC01/02/04/08/16
1K/2K/4K/8K/16K-Bit Serial E2PROM FEATURES
s 400 KHZ I C Bus Compatible* s 1.8 to 6.0Volt Operation s Low Power CMOS Technology s Hardware Write Protect s Page Write Buffer
2
s Self-Timed Write Cycle with Auto-Clear s 1,000,000 Program/Erase Cycles s 100 Year Data Retention s 8-pin DIP, 8-pin SOIC, 8 pin TSSOP or 14-pin
SOIC Package
s Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT24WC01/02/04/08/16 is a 1K/2K/4K/8K/16Kbit Serial CMOS E2PROM internally organized as 128/ 256/512/1024/2048 words of 8 bits each. Catalyst's advanced CMOS technology substantially reduces device power requirements. The CAT24WC01/02 features an 8-byte page write buffer, and the CAT24WC04/08/16 features an 16-byte page write buffer. The device operates via the I2C bus serial interface, has a special write protection feature, and is available in 8-pin DIP, 8-pin SOIC, 8-pin TSSOP or 14-pin SOIC packages.
PIN CONFIGURATION
DIP Package (P)
A0 A1 A2 VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA
BLOCK DIAGRAM
SOIC Package (J14)
NC A0 A1 NC A2 VSS NC 1 2 3 4 5 6 7 14 13 12 11 10 9 8 NC VCC TEST NC SCL SDA NC
5027 FHD F01
EXTERNAL LOAD DOUT ACK VCC VSS WORD ADDRESS BUFFERS COLUMN DECODERS SENSE AMPS SHIFT REGISTERS
SOIC Package (J)
A0 A1 A2 VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA
SDA
START/STOP LOGIC
TSSOP Package (U)
(* Available for 24WC01 and 24WC02 only)
5020 FHD F01
A0 A1 A2 VSS
1 2 3 4
8 7 6 5
XDEC
E2PROM
VCC WP SCL SDA
WP
CONTROL LOGIC
PIN FUNCTIONS
Pin Name A0, A1, A2 SDA SCL WP VCC VSS Function Device Address Inputs Serial Data/Address Serial Clock Write Protect +1.8V to +6.0V Power Supply Ground
I2C Bus Protocol. SCL A0 A1 A2 STATE COUNTERS SLAVE ADDRESS COMPARATORS
DATA IN STORAGE
HIGH VOLTAGE/ TIMING CONTROL
24WCXX F03
* Catalyst Semiconductor is licensed by Philips Corporation to carry the
© 1997 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
Stock No. 21003-03 12/97
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CAT24WC01/02/04/08/16
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ........ 55°C to +125°C Storage Temperature ..... 65°C to +150°C Voltage on Any Pin with Respect to Ground(1) .. 2.0V to +VCC + 2.0V VCC with Respect to Ground ...... 2.0V to +7.0V Package Power Dissipation Capability (Ta = 25°C) .......... 1.0W Lead Soldering Temperature (10 secs) ... 300°C Output Short Circuit Current(2) ...... 100mA RELIABILITY CHARACTERISTICS Symbol NEND(3) TD R
(3)
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
Parameter Endurance Data Retention ESD Susceptibility Latch-up
Min. 1,000,000 100 2000 100
Max.
Units Cycles/Byte Years Volts mA
Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17
VZAP(3) ILTH(3)(4)
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +6.0V, unless otherwise specified.
Limits Symbol I CC ISB(5) I LI ILO V IL V IH V OL1 V OL2 Parameter Power Supply Current Standby Current (VCC = 5.0V) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage (VCC = 3.0V) Output Low Voltage (VCC = 1.8V) 1 VCC x 0.7 Min. Typ. Max. 3 0 10 10 VCC x 0.3 VCC + 0.5 0.4 0.5 Units mA µA µA µA V V V V IOL = 3 mA IOL = 1.5 mA Test Conditions fSCL = 100 KHz VIN = GND or VCC VIN = GND to VCC VOUT = GND to VCC
CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V Symbol CI/O(3) C I N( 3 ) Test Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, SCL, WP) Max. 8 6 Units pF pF Conditions VI/O = 0V VIN = 0V
Note: (1) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from 1V to VCC +1V. (5) Standby Current (ISB) = 0µA (<900nA).
Stock No. 21003-03 12/97
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CAT24WC01/02/04/08/16
A.C. CHARACTERISTICS
VCC = +1.8V to +6.0V, unless otherwise specified.
Read & Write Cycle Limits Symbol Parameter VCC=1.8V - 6V Min. FS C L TI ( 1 ) tAA tBUF(1) tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR(1) tF
(1)
VCC=4.5V - 5.5V Min. Max. 400 200 1 1.2 0.6 1.2 0.6 0.6 0 50 Units kHz ns µs µs µs µs µs µs ns ns 0.3 300 0.6 100 µs ns µs ns
Max. 100 200 3.5
Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs SCL Low to SDA Data Out and ACK Out Time the Bus Must be Free Before a New Transmission Can Start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time (for a Repeated Start Condition) Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time 4 100 4.7 4 4.7 4 4.7 0 50
1 300
tSU:STO tDH
Power-Up Timing(1)(2) Symbol tPUR tPUW Parameter Power-up to Read Operation Power-up to Write Operation Max. 1 1 Units ms ms
Write Cycle Limits Symbol t WR Parameter Write Cycle Time Min. Typ. Max 10 Units ms
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Stock No. 21003-03 12/97
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CAT24WC01/02/04/08/16
FUNCTIONAL DESCRIPTION
The CAT24WC01/02/04/08/16 supports the I2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. Data transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT24WC01/ 02/04/08/16 operates as a Slave device. Both the Master and Slave devices can operate as either transmitter or receiver, but the Master device controls which mode is activated. A maximum of 8 devices (24WC01 and 24WC02), 4 devices (24WC04), 2 devices (24WC08) and 1 device (24WC16) may be connected to the bus as determined by the device address inputs A0, A1, and A2.
PIN DESCRIPTIONS
SCL: Serial Clock The CAT24WC01/02/04/08/16 serial clock input pin is used to clock all data transfers into or out of the device. This is an input pin. SDA: Serial Data/Address The CAT24WC01/02/04/08/16 bidirectional serial data/ address pin is used to transfer data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. A0, A1, A2: Device Address Inputs These inputs set device address when cascading multiple devices. When these pins are left floating the default values are zeros (except for the 24WC01). A maximum of eight devices can be cascaded when
Figure 1. Bus Timing tF
tLOW SCL tSU:STA tHD:STA
tHIGH tLOW
tR
tHD:DAT
tSU:DAT
tSU:STO
SDA IN tAA SDA OUT
5020 FHD F03
tDH
tBUF
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT BYTE n
ACK tWR STOP CONDITION START CONDITION ADDRESS
5020 FHD F04
Figure 3. Start/Stop Timing
SDA
SCL
5020 FHD F05
START BIT
Stock No. 21003-03 12/97
STOP BIT
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CAT24WC01/02/04/08/16
using either 24WC01 or 24WC02 device. All three address pins are used for these densities. If only one 24WC02 is addressed on the bus, all three address pins (A0, A1and A2) can be left floating or connected to VSS. If only one 24WC01 is addressed on the bus, all three address pins (A0, A1and A2) must be connected to VSS. A total of four devices can be addressed on a single bus when using 24WC04 device. Only A1 and A2 address pins are used with this device. The A0 address pin can be tied to VSS or left floating. If only one 24WC04 is being addressed on the bus, the address pins (A1 and A2) can be left floating or connected to VSS. Only two devices can be cascaded when using 24WC08. The only address pin used with this device is A2. The other two address pins and can be tied to VSS or left floating. If only one 24WC08 is being addressed on the bus, the address pin (A2) can be left floating or connected to VSS. The 24WC16 is a stand alone device. In this case, all address pins (A0, A1and A2) can be tied to VSS or left floating. WP: Write Protect If the WP pin is tied to VCC the entire memory array becomes Write Protected (READ only). When the WP pin is tied to VSS or left floating normal read/write operations are allowed to the device. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. START Condition The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT24WC01/02/04/08/16 monitor the SDA and SCL lines and will not respond until this condition is met. STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a START condition. The Master then sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are fixed as 1010 for the CAT24WC01/02/04/08/16 (see Fig. 5). The next three significant bits (A2, A1, A0) are the device address bits and define which device or which part of the device the Master is accessing. Up to eight CAT24WC01/ 02, four CAT24WC04, two CAT24WC08, and one CAT24WC16 may be individually addressed by the system. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. After the Master sends a START condition and the slave address byte, the CAT24WC01/02/04/08/16 monitors the bus and responds with an acknowledge (on the SDA
I2C BUS PROTOCOL
The following defines the features of the I2C bus protocol: (1) Data transfer may be initiated only when the bus is not busy. Figure 4. Acknowledge Timing
SCL FROM MASTER
1
8
9
DATA OUTPUT FROM TRANSMITTER
DATA OUTPUT FROM RECEIVER
5020 FHD F06
START
ACKNOWLEDGE
Stock No. 21003-03 12/97
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Others parts begin by 24
24-1 24-2 24-3 24-4 24-5 24-6
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