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Part: 24WC32
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Preliminary
Preliminary
CAT24WC32/64
CAT24WC32/64
32K/64K-Bit Serial CMOS E2PROM FEATURES
s 400 KHz I2C Bus Compatible* s 1.8 to 6 Volt Read and Write Operation s Cascadable for up to Eight Devices s 32-Byte Page Write Buffer s Self-Timed Write Cycle with Auto-Clear s 8-Pin DIP or 8-Pin SOIC s Schmitt Trigger Inputs for Noise Protection s Zero Standby Current s Commercial, Industrial and Automotive Tem-
perature Ranges
s Write Protection
WP at VIH - Entire Array Protected
s 1,000,000 Program/Erase Cycles s 100 Year Data Retention
DESCRIPTION
The CAT24WC32/64 is a 32K/64K-bit Serial CMOS E2PROM internally organized as 4096/8192 words of 8 bits each. Catalyst's advanced CMOS technology substantially reduces device power requirements. The CAT24WC32/64 features a 32-byte page write buffer. The device operates via the I2C bus serial interface and is available in 8-pin DIP or 8-pin SOIC packages.
PIN CONFIGURATION
DIP Package (P)
A0 A1 A2 VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA
BLOCK DIAGRAM
EXTERNAL LOAD DOUT ACK VCC VSS WORD ADDRESS BUFFERS COLUMN DECODERS 256 SDA START/STOP LOGIC SENSE AMPS SHIFT REGISTERS
SOIC Package (J,K)
A0 A1 A2 VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA
E2PROM XDEC 128/256 128/256 X 256 WP CONTROL LOGIC
24WC32/64 F01
PIN FUNCTIONS
Pin Name A0, A1, A2 SDA SCL WP VCC VSS Function Device Address Inputs Serial Data/Address Serial Clock Write Protect +1.8V to +6V Power Supply Ground
SCL A0 A1 A2
I2C
DATA IN STORAGE
HIGH VOLTAGE/ TIMING CONTROL STATE COUNTERS SLAVE ADDRESS COMPARATORS
24WC32/64 F02
* Catalyst Semiconductor is licensed by Philips Corporation to carry the
© 1997 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
Bus Protocol.
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CAT24WC32/64
Preliminary
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ........ 55°C to +125°C Storage Temperature ..... 65°C to +150°C Voltage on Any Pin with Respect to Ground(1) .. 2.0V to +VCC + 2.0V VCC with Respect to Ground ...... 2.0V to +7.0V Package Power Dissipation Capability (Ta = 25°C) .. 1.0W Lead Soldering Temperature (10 secs) ... 300°C Output Short Circuit Current (2) ...... 100mA RELIABILITY CHARACTERISTICS Symbol NEND TD R ILTH VZAP
(3) (3) (3)
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
Parameter Endurance Data Retention ESD Susceptibility Latch-up
Min. 1,000,000 100 2000 100
Max.
Units Cycles/Byte Years Volts mA
Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17
(3)(4)
D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +6.0V, unless otherwise specified. Limits Symbol ICC ISB(5) ILI ILO VIL VIH VOL1 VOL2 Parameter Power Supply Current Standby Current (VCC = 5V) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage (VCC = +3.0V) Output Low Voltage (VCC = +1.8V) 1 VCC x 0.7 Min. Typ. Max. 3 0 10 10 VCC x 0.3 VCC + 0.5 0.4 0.5 Units mA µA µA µA V V V V IOL = 3.0 mA IOL = 1.5 mA Test Conditions fSCL = 100 KHz VIN = GND or VCC VIN = GND to VCC VOUT = GND to VCC
CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V Symbol CI/O(3) CIN
(3)
Test Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, SCL, WP)
Max. 8 6
Units pF pF
Conditions VI/O = 0V VIN = 0V
Note: (1) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from 1V to VCC +1V. (5) Standby current (ISB ) = 0 µA (<900 nA).
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Preliminary
A.C. CHARACTERISTICS VCC = +1.8V to +6V, unless otherwise specified Output Load is 1 TTL Gate and 100pF Read & Write Cycle Limits Symbol Parameter VCC=1.8V - 6V Min. FS C L TI ( 1 ) tAA tBUF(1) tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR
(1)
CAT24WC32/64
VCC=4.5V - 5.5V Min. Max. 400 200 1 1.2 0.6 1.2 0.6 0.6 0 50 Units kHz ns µs µs µs µs µs µs ns ns 0.3 300 0.6 100 µs ns µs ns
Max. 100 200 3.5
Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs SCL Low to SDA Data Out and ACK Out Time the Bus Must be Free Before a New Transmission Can Start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time (for a Repeated Start Condition) Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time 4 100 4.7 4 4.7 4 4.7 0 50
1 300
tF(1) tSU:STO tDH
Power-Up Timing (1)(2) Symbol t PUR t PUW Parameter Power-Up to Read Operation Power-Up to Write Operation Max. 1 1 Units ms ms
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Write Cycle Limits Symbol t WR Parameter Write Cycle Time Min. Typ. Max 10 Units ms
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
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CAT24WC32/64
Preliminary
SDA: Serial Data/Address The bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. A0, A1, A2: Device Address Inputs These pins are hardwired or left unconnected (for hardware compatibility with CAT24WC16). When hardwired, up to eight CAT24WC32/64s may be addressed on a single bus system (refer to Device Addressing ). When the pins are left unconnected, the default values are zeros. WP: write protect This input, when tied to GND, allows write operations to the entire memory. For CAT24WC32/64 when this pin is tied to Vcc, the entire memory is write protected. When left floating, memory is unprotected.
FUNCTIONAL DESCRIPTION
The CAT24WC32/64 supports the I2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. The transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT24WC32/64 operates as a Slave device. Both the Master device and Slave device can operate as either transmitter or receiver, but the Master device controls which mode is activated.
PIN DESCRIPTIONS
SCL: Serial Clock The serial clock input clocks all data transferred into or out of the device.
Figure 1. Bus Timing
tF tLOW
tHIGH tLOW
tR
SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO
SDA IN tAA SDA OUT
5020 FHD F03
tDH
tBUF
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT BYTE n
ACK tWR STOP CONDITION START CONDITION ADDRESS
5020 FHD F04
Figure 3. Start/Stop Timing
SDA
SCL START BIT
Stock No. 21066-02 12/97
STOP BIT
5020 FHD F05
4
Preliminary
CAT24WC32/64
compare to the hardwired input pins, A2, A1 and A0. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. After the Master sends a START condition and the slave address byte, the CAT24WC32/64 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT24WC32/64 then performs a Read or Write operation depending on the state of the R/W bit. Acknowledge After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The CAT24WC32/64 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte. When the CAT24WC32/64 begins a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT24WC32/64 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. The master must then issue a stop condition to return the CAT24WC32/64 to the standby power mode and place the device in a known state.
I2C BUS PROTOCOL
The features of the I2C bus protocol are defined as follows: (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. START Condition The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT24WC32/64 monitors the SDA and SCL lines and will not respond until this condition is met. STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a START condition. The Master sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are fixed as 1010 (Fig. 5). The next three bits (A2, A1, A0) are the device address bits; up to eight 32K/64K devices may to be connected to the same bus. These bits must
Figure 4. Acknowledge Timing
SCL FROM MASTER 1 8 9
DATA OUTPUT FROM TRANSMITTER
DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE
5020 FHD F06
Figure 5. Slave Address Bits
1 0 1 0 A2 A1 A0 R/W
5027 FHD F07
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