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Part: 25F080A
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NX25F080A
NX25F080A
8M-BIT SERIAL FLASH MEMORY WITH 4-PIN SPI INTERFACE
FEATURES
· Flash Storage for Resource-Limited Systems Ideal for portable/mobile and microcontroller-based applications that store data, voice, and images · On-chip Serial SRAM Dual 536-byte Read/Write SRAM buffers Use in conjunction with or independent of Flash Off-loads RAM-limited microcontrollers · Special Features for Media-Storage Applications Byte-level addressing Transfer or compare sector to SRAM Versatile hardware and software write-protection Alternate oscillator frequency for EMI sensitive applications. In-system electronic part number identification Removable Serial Flash Module package option Serial Flash Development Kit PRELIMINARY JUNE 1999
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· NexFlash Non-volatile Memory Technology Patented single transistor EEPROM memory High-density, low-voltage & power, cost-effective Small DOS compatible sectors, 512+24 bytes 10K/100K write cycles, ten years data retention
· Ultra-low Power for Battery-Operation Single 5V or 3V supply for Read, Erase/Write Low frequency read command for very low power 1 µA standby current, 5 mA active @ 3V (typical) No pre-erase. Erase/Write time of 5 ms/sector @5V (typical) ensures efficient battery use · 4-pin SPI Serial Interface Easily interfaces to popular microcontrollers Clock operation as fast as 16 MHz
DESCRIPTION
The NX25F080A Serial Flash memory provides a storage solution for systems limited in power, pins, space, hardware, and firmware resources. They are ideal for media-storage applications that store data, voice, and images in a portable or mobile environment. Using NexFlash's patented single transistor EEPROM cell, the NX25F080A offers a high-density, low-voltage, low-power, and cost-effective non-volatile memory solution. The NX25F080A operates on a single 5V or 3V (2.7V-3.6V) supply for Read and Erase/Write with typical current consumption as low as 5 mA active and less than 1 µA standby. Sector Erase/Write speeds as fast as 5 ms increase system performance, minimize power-on time, and maximize battery life. The NX25F080A has 8M-bits of flash memory organized as 2,048 DOS-compatible sectors of 536 bytes each. Each sector is individually addressable through basic ser i a l - clocked commands. The 4-pin SPI serial interface works directly with popular microcontrollers. Special features i n c l u d e : serial SRAM, byte-level addressing, double-buffered sector writes, transfer or compare sector to SRAM, versatile hardware and software write protection, user-selected oscillator frequency, electronic part number, and removable Serial Flash Module package option. Development is supported with the PC-based Serial Flash Development Kit.
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This document contains PRELIMINARY INFORMATION. NexFlash reserves the right to make changes to its product at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1998, NexFlash Technologies, Inc.
NexFlash Technologies, Inc.
PRELIMINARY NXSF013C-0699
06/11/99 ©
1
NX25F080A
FUNCTIONAL OVERVIEW
An architectural block diagram of the NX25F080A is shown in Figure 2. Key elements of the architecture include: · · · · · · SPI Interface and Command Set Logic Serial Flash Memory Array Serial SRAM and Program Buffer Write Protection Logic Configuration and Status Registers Device Information Sector
DEVICE INFORMATION SECTOR (READ ONLY)
ROW DECODE (1024 OR 2048 SECTORS)
WRITE PROTECT LOGIC (16 BLOCKS OF 128 SECTORS EACH)
WP
WRITE CONTROL LOGIC
16
8 MEGABIT SERIAL FLASH MEMORY ARRAY
2048 BYTE-ADDRESSABLE SECTORS OF 536 BYTES EACH
HOLD OR R/B
HOLD OR READ/BUSY LOGIC
CONFIGURATION REGISTER STATUS REGISTER
4288 PROGRAM BUFFER (536 BYTES) 4288 SRAM (536 BYTES) 8 8 8
HIGH-VOLTAGE GENERATORS
10 SCK CS SI SO SPI COMMAND AND CONTROL LOGIC
SECTOR-ADDRESS LATCH
DATA
COLUMN DECODE, SENSE AMP LATCH AND DATA COMPARE LOGIC
BYTE-ADDRESS LATCH/COUNTER
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Figure 2. NX25F080A Architectural Block Diagram
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NexFlash Technologies, Inc.
PRELIMINARY NXSF013C-0699
06/11/99 ©
NX25F080A
Pin Descriptions
Package The NX25F080A is available in a 24/28-pin TSOP (Type II) surface mount package. See Figure 3 and Table 1 for pin assignments. All interface and supply pins are on one side of the package. The "No Connect" (NC) pins are not connected to the device, allowing the pads and the area around them to be used for routing PCB system traces. The 50 mil pin-to-pin spacing of the package eases assembly and pre-programming compared to other Flash devices that use 25 mil spacing. The NX25F080A is also available in a cost-effective and space-efficient removable Serial Flash Module package (see NX25Mxxx data sheet). Serial Data Input (SI) The SPI bus Serial Data Input (SI) provides a means for data to be written to (shifted into) the device. Serial Data Output (SO) The SPI bus Serial Data Output (SO) provides a means for data to be read from (shifted out of) the device during a read operation. When the device is deselected (CS=1 or HOLD=0) the SO pin is in a high-impedance state. Serial Clock (SCK) All commands and data written to the Serial Input (SI) are clocked relative to the rising edge of the Serial Clock (SCK). By default all data read from the Serial Data Output (SO) is clocked relative to the falling edge of SCK, allowing compatibility with standard SPI systems. The user may specify reading relative to the rising edge of SCK by changing the setting of the RCE bit in the Configuration Register (see Figure 6). Clock rates of up to 16 MHz for 5V devices and up to 8 MHz for 3V devices are supported. Chip Select (CS) The NX25F080A is selected for operation when the Chip Select Input (CS) is asserted low. Upon power-up, an initial low to high transition of CS is required before any command sequence will be acknowledged. The device can be de-selected to a non-active state when CS is brought high. Once deselected, the SO pin will enter a high-impedance state and power consumption will decrease to standby levels unless programming is in process, in which case standby will resume when programming is complete. Write Protect (WP) The Write Protect Input (WP) works in conjunction with the write protect range set in the Configuration Register bits. When WP is asserted (active LOW) the entire Flash memory array is write protected. When HIGH, any Flash memory sector can be written to unless its address is within the write protect range that is set in the Configuration Register. Hold or Ready/Busy (HOLD or R/B) This multi-function pin can serve either as a Hold Input (HOLD) or as a Ready-Busy Output (R/B). The pin function is user-programmable via the non-volatile Configuration Register. Factory-programmed as a no connect, the pin can be reconfigured as a Ready/Busy output or as a Hold input by setting the Configuration Register. See the Configuration Register section of this data sheet for further details. Warning: this pin is tied low in the Serial Flash Module and must be left as a no connect (NC). Power Supply Pins (Vcc and Gnd) The NX25F080A support single power supply read and erase/write operations in 5V and 3V Vcc versions. Typical active power is as low as 5 mA for 3V versions with standby current in the 1 µA range.
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HOLD R/B SCK SO Vcc NC NC
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28 27 26 25 24 23
NC NC NC NC NC NC
NC NC CS WP SI GND
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20 19 18 17 16 15
NC NC NC NC NC NC
Table 1. Pin Descriptions SI SO SCK CS WP Hold, R/B Vcc Serial Data Input Serial Data Output Serial Clock Input Chip Select Input Write Protect Input Hold Input or Read Busy Output Power Supply
Figure 3. NX25F080A Pin Assignments
NexFlash Technologies, Inc.
PRELIMINARY NXSF013C-0699
06/11/99 ©
3
NX25F080A
Serial Flash Memory Array
The NX25F080A Serial Flash memory array is organized as 2,048 sectors of 536 bytes (4,288 bits) each, as shown in Figure 4. The 536 bytes offer a convenient format for applications that store and transfer data in a DOS compatible sector size of 512 bytes. The additional 24 bytes per sector are provided for user-specified sector management such as header, checksum, CRC, or other related application requirements. T h e Serial Flash memory of the NX25F080A is byte-addressable. That is, each sector is individually addressable and each byte within a sector is individually addressable. This allows a single byte, or specified sequence of bytes, to be read without having to clock an entire 536-byte sector out of the device. Data can be read directly from a sector in the flash memory array by issuing a Read from Sector command from the SPI bus. Data can be written to a sector in the Flash memory array by means of the Serial SRAM using a Write to S e c t o r command or a Transfer SRAM to Sector command. After a sector has been written, the memory array will become busy while it is programming the specified non-volatile memory cells of that sector. This busy time will not exceed tWP (~5 ms for 5V devices), during which time the Flash array is unavailable for read or write access. The device can be tested to determine the array's availability using the Ready/Busy status that is available during most read commands, via the Status Register, or on the Ready/Busy pin. Note that the SRAM is always available, even when the memory array is busy. See the Serial SRAM section for more details. The NX25F080A does not require pre-erase. Instead, the device incorporates an auto-erase-before-write feature that automatically erases the addressed sector at the beginning of the write operation. This allows for fast and consistent programming times. It also simplifies firmware support by eliminating the need for a separate pre-erase algorithm and the complex management of disproportional erase and write block sizes commonly found in other devices.
Sector Address: IS25F080A S[10:0]
Sector 2047 7FFH Sector 2046 7FEH Byte 0 000H Byte 0 000H Byte1 001H Byte1 001H
Byte Address: B[9:0]
Byte 2-533 002H-215H Byte 2-533 002H-215H Byte 534 216H Byte 534 216H Byte 535 217H Byte 535 217H
Sector 3-2045 003H-7FDH
8M-bit Serial Flash Memory Array 2048 Byte-Addressable Sectors of 536-Bytes each
Sector 1 001H Sector 0 000H
Byte 0 000H Byte 0 000H
Byte 1 001H Byte 1 001H
Byte 2-533 002H-215H Byte 2-533 002H-215H
Byte 534 216H Byte 534 216H
Byte 535 217H Byte 535 217H
Figure 4. NX25F080A Serial Flash Memory Array 4
NexFlash Technologies, Inc.
PRELIMINARY NXSF013C-0699
06/11/99 ©
NX25F080A
Serial SRAM and Program Buffer
One of the most powerful features of the NX25F080A is the integrated Serial SRAM and its associated Program Buffer. Together, the 536-byte Serial SRAM and 536-byte Program Buffer provide up to 1072 bytes of usable SRAM storage. The SRAM can be used in conjunction with the Flash memory or independently. The main purpose of the Serial SRAM is to serve as the primary buffer for sector data to be written into the Serial Flash memory array. Using the Write to Sector command, data is first shifted into the SRAM from the SPI bus. When the command sequence has been completed, the entire 536-bytes is transferred to the Program Buffer. The Program Buffer supports the array during the Erase/Write cycle (tWP), freeing the SRAM to accept new data. This double-buffering scheme increases erase/ write transfer rates and can eliminate the need for external RAM buffers (Figure 5). The SRAM is fully byte-addressable. Thus, the entire 536-bytes, a single byte, or a sequence of bytes can be read from, or written to the SRAM. This allows the SRAM to be used as a temporary work area for read-modify-write operations prior to a sector write. The Transfer Sector to SRAM command allows the contents of a specified sector of Flash memory to be moved to the SRAM. This can be useful when only a portion of a sector needs to be altered. In this case the sector is first transferred to the SRAM, where modifications are made using the Write to SRAM command. Once complete, a Transfer SRAM to Sector command is used to update the sector.
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DEVICE INFORMATION SECTOR
READ FROM DEVICE INFORMATION SECTOR READ FROM SECTOR
SERIAL FLASH MEMORY ARRAY
CONFIGURATION REGISTER STATUS REGISTER
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TRANSFER SECTOR TO SRAM
2048 BYTE-ADDRESSABLE SECTORS OF 536-BYTES EACH
SCK CS SI SO
SPI COMMAND AND CONTROL LOGIC COMPARE SECTOR TO SRAM READ FROM PROGRAM BUFFER
TRANSFER SRAM TO SECTOR (VIA PROGRAM BUFFER)
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TRANSFER SRAM TO PROGRAM BUFFER
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READ FROM OR WRITE TO SRAM
WRITE TO SECTOR (VIA SRAM & PROGRAM BUFFER)
PROGRAM
BUFFER
SERIAL SRAM
TRANSFER PROGRAM BUFFER TO SRAM
Note: 1. A single byte, several bytes, or all bytes of a Flash sector, the SRAM, or Program Buffer may be addressed. 2. All double lines represent implied connections or actions.
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Figure 5. Command Relationships of the SPI Interface, Serial Flash Memory Array, SRAM and Program Buffer
NexFlash Technologies, Inc.
PRELIMINARY NXSF013C-0699
06/11/99 ©
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