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Part: 271001
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M27C1001
1 Megabit (128K x 8) UV EPROM and OTP ROM
VERY FAST ACCESS TIME: 45ns COMPATIBLE with HIGH SPEED MICROPROCESSORS, ZERO WAIT STATE LOW POWER "CMOS" CONSUMPTION: Active Current 30mA Standby Current 100µA PROGRAMMING VOLTAGE: 12.75V ELECTRONIC SIGNATURE for AUTOMATED PROGRAMMING PROGRAMMING TIMES of AROUND 12sec. (PRESTO II ALGORITHM)
28
1
FDIP32W (F)
LCCC32W (L)
DESCRIPTION The M27C1001 is a high speed 1 Megabit UV erasable and electrically programmable memory EPROM ideally suited for microprocessor systems req u irin g lar ge p ro g ra ms . I t is o rg an ize d a s 131,07 2 by 8 bits. The 32 pin Window Ceramic Frit-Seal Dual-in-Line and Leadless Chip Carrier packages have transparent lids which allow the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the device by following th e programming procedure. For applications where the content is programmed only one time and erasure is no t required, the M27C1001 is offered in both Plastic Dual-in-Line, Plastic Leaded Chip Carrier and Plastic Thin Small Outline packages. Table 1. Signal Names
A0 - A16 Q0 - Q7 E G P VPP VCC VSS Address Inputs Data Outputs Chip Enable Output Enable Program Program Supply Supply Voltage Ground
PLCC32 (C)
TSOP32 (N) 8 x 20mm
Figure 1. Logic Diagram
VCC
VPP
17 A0-A16
8 Q0-Q7
P E G
M27C1001
VSS
AI00710B
May 1995
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M27C1001
Figure 2A. DIP Pin Connections
VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 VSS 1 2 3 4 5 6 7 8 M27C1001 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC P NC A14 A13 A8 A9 A11 G A10 E Q7 Q6 Q5 Q4 Q3
Figure 2B. LCC Pin Connections
A 12 A 15 A 16 V PP V CC P NC 1 32 A7 A6 A5 A4 A3 A2 A1 A0 Q0 A14 A13 A8 A9 A11 G A10 E Q7 9 M27C1001 25 17 V SS Q3 Q4 Q5 Q6
AI00712
AI00711
Warning: NC = Not Connected.
Warning: NC = Not Connected.
Figure 2C. TSOP Pin Connections
A11 A9 A8 A13 A14 NC P VCC VPP A16 A15 A12 A7 A6 A5 A4 1 32 G A10 E Q7 Q6 Q5 Q4 Q3 VSS Q2 Q1 Q0 A0 A1 A2 A3
Read Mode The M27C1001 has two control functions, both of which must b e logically active in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, the address access time (tAVQV) is equal to the delay from E to output (tELQV). Data is available at the output after a delay of tGLQV from the falling edge of G, assuming that E has been low and the addresses have been stable for at least tAVQV-tGLQV. Standby Mode The M27C1001 has a standby mode which reduces the active current from 30mA to 100µA. The M27C1001 is placed in the standby mode by applying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the G input. Two Line Output Control
8 9
M27C1001 (Normal)
25 24
16
17
AI01151B
Warning: NC = Not Connected.
DEVICE OPERATION The modes of operation of the M27C1001 are listed in the Operating Modes table. A single 5V power supply is required in the read mode. All inputs are TTL levels except f or VPP and 12V on A9 for Electronic Signature.
Because EPROMs are usually used in larger memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows : a. the lowest possible memory power dissipation, b. complete assurance that output bus contention will not occur.
2/15
Q1 Q2
M27C1001
Table 2. Absolute Maximum Ratings (1)
Symbo l TA TBIAS TSTG VIO
(2)
Parameter Ambient Operating Temperature Temperature Under Bias Storage Temperature Input or Outp ut Voltages (except A9) Supply Voltage A9 Voltage Program Supply Voltage
Value 40 to 125 50 to 125 65 to 150 2 to 7 2 to 7 2 to 13.5 2 to 14
Unit °C °C °C V V V V
VCC VA9
(2)
VPP
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents. 2. Minimum DC voltage on Input or Output is 0.5V with possible undershoot to 2.0V for a period less than 20ns. Maximum DC voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns.
Table 3. Operating Modes
Mode Read Output Disable Program Verify Program Inhibit Standby Electronic Signature
Note: X = VIH or VIL, VID = 12V ± 0.5V
E VIL VIL VIL VIL VIH VIH VIL
G VI L VIH VIH VI L X X VI L
P X X VIL Pulse VIH X X VIH
A9 X X X X X X VI D
VPP VCC or VSS VCC or VSS VPP VPP VPP VCC or VSS VCC
Q0 - Q7 Data Out Hi-Z Data In Data Out Hi-Z Hi-Z Codes
Table 4. Electronic Signature
Identifier Manufacturer's Code Device Code A0 VIL VIH Q7 0 0 Q6 0 0 Q5 1 0 Q4 0 0 Q3 0 0 Q2 0 1 Q1 0 0 Q0 0 1 Hex Data 20h 05h
DEVICE OPERATION (cont'd) For the most efficient use of these two control lines, E should be decode d a nd used as the primary device selecting function, while G should be made a common connection t o all devices in the array and connected to the REA D line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device.
System Considerations The power switching characteristics of Advanced CMOS EPROMs require careful decoupling of the devices. The supply current, I CC, has three segments th at are o f interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the falling and rising edges of E. The magnitude of the transient current peaks is depende nt on the capacitive and inductive loading of the device at the output.
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M27C1001
AC MEASUREMENT CONDITIONS
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 20ns 0.4 to 2.4V 0.8 to 2.0V
Figure 4. AC Testing Load Circuit
1.3V
1N914
Note that Output Hi-Z is defined as the point where data is no longer driven.
Figure 3. AC Testing Input Output Waveforms
DEVICE UNDER TEST 2.0V 0.8V
AI00826
3.3k
OUT CL = 100pF
2.4V
0.4V
CL includes JIG capacitance
AI00828
Note: For 45ns and 55ns class: input pulse voltages are 0V to 3V, input output test points are at 1.5V, CL is 30 pF.
Table 5. Capacitance (1) (TA = 25 °C, f = 1 MHz )
Symbol C IN C OUT Parameter Input Capacitance Output Capacitance Test Cond ition VIN = 0V VOUT = 0V Min Max 6 12 Unit pF pF
Note: 1. Sampled only, not 100% tested.
Table 6. Read Mode DC Characteristics (1) (TA = 0 to 70 °C, 40 to 85 °C or 40 to 125 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
Symbol ILI ILO ICC ICC1 ICC2 IPP VIL VIH
(2)
Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Program Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage TTL Output High Voltage C MOS
Test Cond ition 0V VIN VCC 0V VOUT VCC E = VIL, G = VIL, IOUT = 0mA, f = 5MHz E = VIH E > VCC 0.2V VPP = VCC
Min
Max ±10 ±10 30 1 100 10
Unit µA µA mA mA µA µA V V V V V
0.3 2 IOL = 2.1mA IOH = 400µA IOH = 100µA 2.4 VCC 0.7V
0.8 VC C + 1 0.4
VOL VOH
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Maximum DC voltage on Output is VCC +0.5V.
4/15
M27C1001
Table 7A. Read Mode AC Characteristics (1) (TA = 0 to 70 °C, 40 to 85 °C or 40 to 125 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
M 27C1001 Symbol Alt Parameter Test Con dition -45 Min tAVQV tELQV tGLQV tEHQZ
(2) (3 )
-55
(3)
-60 Min Max 60 60 30 0 0 0 30 30 0 0 0
-70 Min M ax 70 70 35 30 30
Unit
M ax Min 45 45 25
Max 55 55 30
tACC tCE tOE tDF tDF tOH
Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition
E = VIL, G = VIL G = VIL E = VI L G = VIL E = VI L E = VIL, G = VIL 0 0 0
ns ns ns ns ns ns
25 25
0 0 0
25 25
tGHQZ (2) tAXQX
Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Sampled only, not 100% tested. 3. See specific AC Measurament Condition for -45 and -55 classes.
Table 7B. Read Mode AC Characteristics (1) (TA = 0 to 70 °C, 40 to 85 °C or 40 to 125 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
M 27C1001 Symbol Alt Parameter Test Con dition -80 Min tAVQV tELQV tGLQV tEHQZ (2) tGHQZ
(2)
-90 Max 90 90 45 0 0 0 30 30 0 0 0
-10 Min Max 100 100 50 30 30
-12/-15/ -20/-25 Min M ax 120 120 60 0 0 0 40 40
Unit
M ax Min 80 80 40
tACC tCE tOE tDF tDF tOH
Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition
E = VIL, G = VIL G = VIL E = VI L G = VIL E = VI L E = VIL, G = VIL 0 0 0
ns ns ns ns ns ns
30 30
tAXQX
Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Sampled only, not 100% tested.
5/15
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