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Details, datasheet, quote on part number:27128
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Datasheet text preview:
M27128A
NMOS 128K (16K x 8) UV EPROM
FAST ACCESS TIME: 200ns EXTENDED TEMPERATURE RANGE SINGLE 5 V SUPPLY VOLTAGE LOW STANDBY CURRENT: 40mA max TTL COMPATIBLE DURING READ and PROGRAM FAST PROGRAMMING ALGORITHM ELECTRONIC SIGNATURE PROGRAMMING VOLTAGE: 12V
28
1
FDIP28W (F )
DESCRIPTION The M27128A is a 131,07 2 bit UV erasable and electrically programmable memory EPROM. I t is organized as 16,384 words by 8 bits. The M27128A is housed in a 28 Pin Window Ceramic Frit-Seal Dual-in-Line package. The transparent lid allows the user to expose the chip to ultraviolet light to erase the bi t pattern. A new pattern can then be written to the device by following the programming procedure.
Figure 1. Logic Diagram
VCC
VPP
14 A0-A13
8 Q0-Q7
Table 1. Signal Names
A0 - A13 Q0 - Q7 E G P VPP VCC VSS Address Inputs Data Outputs Chip Enable Output Enable Program Program Supply Supply Voltage Ground
P E G
M27128A
VSS
AI00769B
March 1995
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M27128A
Table 2. Absolute Maximum Ratings
Symbol TA TBIAS TSTG VIO VCC VA9 VPP Parameter Ambient Operating Temperature Temperature Under Bias Storage Temperature Input or Output Voltages Supply Voltage A9 Voltage Program Supply grade 1 grade 6 grade 1 grade 6 Value 0 to 70 40 to 85 10 to 80 50 to 95 65 to 125 0.6 to 6.25 0.6 to 6.25 0.6 to 13.5 0.6 to 14 Unit °C °C °C V V V V
Note: Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are s tress ratings only and operation of t he device at th ese or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents.
Figure 2. DIP Pin Connections
VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 VSS
1 2 3 4 5 6 7 M27128A 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC P A13 A8 A9 A11 G A10 E Q7 Q6 Q5 Q4 Q3
AI00770
DEVICE OPERATION The seven modes of operation of the M27128A are listed in the Operating Modes table. A single 5V power supply is required in the read mode. All inputs are TTL levels except for VP P and 12V on A9 for Electronic Signature.
Read Mode The M27128A has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used t o gate data to the output pins, independent of device selection. Assuming that the addresses are stable, address access time (tAVQV) is equal to the delay from E to output (tELQ V). Data is available at the outputs after the falling edge of G, assuming that E has been low and the addresses have been stable for at least tAVQV-tGLQV. Standby Mode The M27128A has a standby mode which reduces the maximum active power current f rom 85mA t o 40mA. The M27128 A is placed in the standby mode by applying a TTL high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independe nt of the G input. Two Line Output Control Because EPROMs are usually used in larger memory arrays, this product features a 2 line control function which accommodates the use o f multiple memory connection. The two line control function allows: a. the lowest possible memory power dissipation, b. complete assurance that output bus contention will not occur.
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M27128A
DEVICE OPERATION (cont'd) For the most efficient use of these two control lines, E should be decoded and used as the primary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device. System Considerations T h e p o we r s wit c h in g c h a ra ct e ri s t ic s o f f a s t EPROMs require careful decoupling of the devices. The supply current, I CC, has three segments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks tha t are produced by the falling and rising edges of E. The magnitude o f this transient current peaks is depend ent on the capacitive and inductive loading of the device at the output. The associated transient voltage peaks can be suppressed by complying with the two line output control and by properly selected decoup ling capacitors. I t is recommended that a 1µF ceramic capacitor be used on every device between VC C and VS S. This should be a high frequency capacitor of low inherent inductance and should be placed as close to the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be used between VCC and GND for every eight devices. The bulk capacitor should be located near the power supply connection point. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces. Programming When delivered (and after each erasure for UV EPPROM), all bits of the M27128A are in the "1" state. Data is introduced by selectively programming "0s" into the desired bit locations. Although only "0s" will be programmed, both "1s" and "0s" can be present in the data word. The only way to change a "0" to a "1" is by ultraviolet light erasure. The M27128A is in the programming mode when VPP input is at 12.5V and E and P are at TTL low. The data to be programmed is applied 8 bits in parallel, to the data output pins. The levels required for the address and data inputs are TTL. Fast Programming Algorithm Fast Programm ing Algo rithm ra pidly programs M27128A EPROMs using an efficient and reliable method suited to the production programming environment. Programming reliability is also ensured as the incremental program margin of each byte is
Table 3. Operating Modes
Mode Read Output Disable Program Verify Program Inhibit Standby Electronic Signature
Note: X = VIH or VIL, VID = 12V ± 0.5%.
E VIL VIL VIL VIL VI H VI H VIL
G VIL VIH VIH VIL X X VIL
P VIH VIH VIL Pulse VIH X X VIH
A9 X X X X X X VID
VPP VCC VCC VPP VPP VPP VCC VCC
Q0 - Q7 Data Out Hi-Z Data In Data Out Hi-Z Hi-Z Codes Out
Table 4. Electronic Signature
Identifier Manufacturer's Code Device Code A0 VIL VI H Q7 0 1 Q6 0 0 Q5 1 0 Q4 0 0 Q3 0 1 Q2 0 0 Q1 0 0 Q0 0 1 Hex Data 20h 89h
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M27128A
AC MEASUREMENT CONDITIONS
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 20ns 0.45V to 2.4V 0.8V to 2.0 V
Figure 4. AC Testing Load Circuit
1.3V
1N914
Note that Output Hi-Z is defined as the point where data is no longer driven.
Figure 3. AC Testing Input Output Waveforms
DEVICE UNDER TEST 2.0V 0.8V
AI00827
3.3k
OUT CL = 100pF
2.4V
0.45V
CL includes JIG capacitance
AI00828
Table 5. Capacitance (1) (TA = 25 °C, f = 1 MHz )
Symbol C IN C OUT Parameter Input Capacitance Output Capacitance Test C ondition VI N = 0V VOUT = 0V M in = = Max 6 12 Unit pF pF
Note: 1. Sampled only, not 100% tested.
Figure 5. Read Mode AC Waveforms
A0-A13 tAVQV E tGLQV G tELQV Q0-Q7
VALID tAXQX
tEHQZ
tGHQZ Hi-Z DATA OUT
AI00771
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M27128A
Table 6. Read Mode DC Characteristics (1) (TA = 0 to 70 °C or 40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VP P = VCC)
Symb ol ILI IL O ICC ICC1 IPP VIL VIH VOL VOH Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) Program Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 2.1mA IOH = 400µA Test Condition 0 VIN VCC VOUT = VCC E = VIL, G = VIL E = VIH VPP = VCC 0.1 2 = 2.4 Min Max ±10 ±10 75 35 5 0.8 VCC + 1 0.45 Unit µA µA mA mA mA V V V V
Note: 1. VCC must be applied simul taneously with or before VPP and removed simultaneously or after VPP.
Table 7. Read Mode AC Characteristics (1) (TA = 0 to 70 °C or 40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
Symbol Alt Parameter Test Condition M27128A -2, -20 M in tAVQV tELQV tGLQV tEHQZ
(2 )
blank, -25 Min Max 250 250 100 0 0 0 60 60
-3, -30 Min Max 300 300 120 0 0 0 105 105 0 0 0 Min
-4 Max 450 450 150 130 130
Unit
Max 200 200 75
tACC tCE tOE tDF tDF tOH
Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Outpu t Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition
E = VIL, G = VIL G = VIL E = VIL G = VIL E = VIL E = VIL, G = VIL 0 0 0
ns ns ns ns ns ns
55 55
tGHQZ (2) tAXQX
Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Sampled only, not 100% tested.
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