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Part: 28101
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Datasheet: Download 28101 datasheet File size : 81 kB
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M28F101
1 Megabit (128K x 8, Chip Erase) FLASH MEMORY
FAST ACCESS TIME: 70ns LOW POWER CONSUMPTION Standby Current: 100µA Max 10,000 ERASE/PROGRAM CYCLES 12V PROGRAMMING VOLTAGE TYPICAL BYTE PROGRAMING TIME 10µs (PRESTO F ALGORITHM) ELECTRICAL CHIP ERASE in 1s RANGE INTEGRATED ERASE/PROGRAM-STOP TIMER OTP COMPATIBLE PACKAGES and PINOUTS EXTENDED TEMPERATURE RANGES
32
1
PDIP32 (P)
PLCC32 (K)
TSO P32 (N) 8 x 20 mm
DESCRIPTION The M28F101 FLASH Memory is a non-volatile memory which may be erased electrically at the chip level an d programmed byte-by-byte. It is organised as 128K bytes of 8 bits. It uses a command register architecture to select the operating modes and thus provides a simple microprocessor interface. The M28F101 FLASH Memory is suitable for applications where the memory has to be reprogrammed in t he equipment. The access time of 100ns makes the device suitable for use in high speed microprocessor systems.
Figure 1. Logic Diagram
VCC
VPP
17 A0-A16
8 DQ0-DQ7
Table 1. Signal Names
A0 - A16 DQ0 - D Q7 E G W VPP VCC VSS May 1996 Address Inputs Data Inputs / Outputs Chip Enable Output Enable Write Enable Program Supply Supply Voltage Ground
W E G
M28F101
VSS
AI00666B
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M28F101
Figure 2A. DIP Pin Connections
Figure 2B. LCC Pin Connections
VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 2 3 4 5 6 7 8 M28F101 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC W NC A14 A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
A7 A6 A5 A4 A3 A2 A1 A0 DQ0
A 12 A 15 A 16 VPP VCC W NC 1 32 A14 A13 A8 A9 A11 G A10 E DQ7 9 M28F101 25 17 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6
AI00668
AI00667
Warning: NC = Not Connected
Warning: NC = Not Connected
Figure 2C. TSOP Pin Connections
Figure 2D. TSOP Reverse Pin Connections
A11 A9 A8 A13 A14 NC W VCC VPP A16 A15 A12 A7 A6 A5 A4
1
32
8 9
M28F101 (Normal)
25 24
16
17
AI00669B
G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
1
32
8 9
M28F101 (Reverse)
25 24
16
17
AI00670C
A11 A9 A8 A13 A14 NC W VCC VPP A16 A15 A12 A7 A6 A5 A4
Warning: NC = Not Connected
Warning: NC = Not Connected
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M28F101
Table 2. Absolute Maximum Ratings
Symbol TA TSTG VIO VC C VA9 VPP Parameter Am bient Operating Temperature Storage Temperature Input or Output Voltages Supply Voltage A9 Voltage Program Supply Voltage, during Erase or Programming Value 40 to 125 65 to 150 0.6 to 7 0.6 to 7 0.6 to 13.5 0.6 to 14 Unit °C °C V V V V
Note: Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents.
DEVICE OPERATION The M28F101 FLASH Memory employs a technology similar to a 1 Megabit EPROM but adds to the device functionality by providing e lectrical erasure and programming. These functions are managed by a command register. The functions that are addressed via the command register depend on the voltage applied to the VPP, program voltage, input. When VPP is less than o r equal to 6.5V, the command register is disabled and M28F101 functions as a read only memory providing operating modes similar to an EPROM (Read, Output Disable, Electronic Signature Read and Standby). When VPP is raised to 12V the command regsiter is enabled and this provides, in addition, Erase and Program operations. READ ONLY MODES, VPP 6.5V For all Read Only Modes, except Standby Mode, the Write Enable input W should be High. In the Standb y Mode this input is don't care. Read Mode. The M28F101 has two enable inputs, E and G, both o f which must be Low in order to output data from the memory. The Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data on to the output, indepen dant of the device selection. Standby Mode. In the Standb y Mode the maximum supply current is reduced. The device is placed in the Standby Mode by applying a High to the Chip Enable (E) input. When in t he Standby Mode the outputs are in a high impedance state, indepen dant of the Output Enable (G) input.
Output Disable Mode. When the Output Enable (G) is High the outputs are in a high impedance state. Electronic Signature Mode. This mode allows the read out of two binary codes from the device which identify the manufacturer and device type. This mode is intended for use by programming equipment to automatically select the correct erase and programming algorithms. The Electronic Signature Mode is active when a high voltage (11.5V to 13V) is applied to address line A9 with E and G Low. With A0 Low the output data is the manufacturer code, when A0 is High the output is the device type code. All other address lines should be maintained Low while reading the codes. The electronic signature may also be accessed in Read/Write modes. READ/WRITE MODES, 11.4V VP P 12.6V When VPP is High both read and write operations may be performed. These are defined by the contents of an internal command register. Commands may be written to this register to set-up and execute, Erase, Erase Verify, Program, Program Verify and Reset modes. Each of these modes needs 2 cycles. Every mode starts with a write operation to set-up the command, this is followed by either read or write operation s. The device expects the first cycle to be a write operation and does not corrupt data at any location in memory. Read mode is set-up with one cycle only and may be followed by any number of read operations to output data. Electronic Signature Read mode is set-up with one cycle and followed by a read cycle to output the manufacturer or device codes.
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M28F101
Table 3. Operations
VPP Read Only VPPL
(1)
Operation Read Output Disable Standby Electronic Signature
E VIL VIL VIH VIL VIL VIL VIL VIH
G VIL VIH X VIL VIL VIH VIH X
W VIH VIH X VIH VIH VIL Pulse VIH X
A9 A9 X X VID A9 A9 X X
DQ0 - D Q7 Data Output Hi-Z Hi-Z Codes Data Output Data Input Hi-Z Hi-Z
Read/Write
(2)
VPPH
Read Write Output Disable Standby
Notes: 1. X = VIL or VIH 2. Refer also to the Command Table
Table 4. Electronic Signature
Identifier M anufacturer's Code D evice Code A0 VIL VIH DQ7 0 0 DQ6 0 0 DQ5 1 0 DQ4 0 0 DQ3 0 0 DQ2 0 1 DQ1 0 1 DQ0 0 1 Hex Data 20h 07h
Table 5. Commands (1)
Command Read Electronic Signature Setup Erase/ Erase Erase Verify Setup Program/ Program Program Verify Reset
Note: 1. X = VIL or VIH
Cycles Operation 1 2 Write Write Write
1st Cycle A0-A16 X X X DQ0-DQ7 00h 90h 20h Write Read Read Operation
2n d Cycle A0-A16 DQ0-DQ7
00000h 00001h
20h 07h
2 2 2 2 2
X X
20h Data Output
Write Write
A0-A16 X
0A0h 40h
Read
Write Write Write X X 0C0h 0FFh Read Write
A0-A16 X X
Data Input Data Output 0FFh
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M28F101
READ/WRITE MODES (cont'd) A write to the command register is made by bringing W Low while E is Low. The falling edge of W latches Addresses, while the rising edge latches Data, which are used for those commands that require address inputs, command input o r provide data output. The supply voltage VCC and the program voltage VPP can be applied in any order. When the device is powered up or when VP P is 6.5V the contents of the command register default to 00h, thus automatically setting-up Read operations. In addition a specific command may be used to set the command register to 00h for reading the memory. The system designer may chose to provide a constant high VPP and use the register commands for all operations, or to switch the VP P from low to high only when needing to erase or program the memory. All command register access is inhibited when VCC falls below the Erase/Write Lockout Voltage (VLKO) of 2 .5V. If the device is deselected during Erasure, Programming o r Verification it will draw active supply currents until the operations are terminated. The device is protected against stress caused by long erase or program times. If the end of Erase or Programming operations are not terminated by a Verify cycle within a maximum time permitted, an internal stop timer automatically s tops the operation. The device remains in an inactive state, ready to start a Verify or Reset Mode operation.
Table 6. AC Measurement Conditions
SRAM Interface Levels Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 10ns 0 to 3V 1.5V EPROM Interface Levels 10ns 0.45V to 2.4V 0.8V and 2V
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
SRAM Interface 3V 1.5V 0V DEVICE UNDER TEST 2.0V 0.8V
AI01275
1N914
3.3k
EPROM Interface 2.4V
OUT CL = 30pF or 100pF
0.45V
CL = 30pF for SRAM Interface CL = 100pF for EPROM Interface CL includes JIG capacitance
AI01276
Table 7. Capacitance (1) (TA = 25 °C, f = 1 MHz )
Symbol CI N COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 12 Un it pF pF
Note: 1. Sampled only, not 100% test.ed
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