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Part: 28256
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M28F256
256K (32K x 8, Chip Erase) FLASH MEMORY
FAST ACCESS TIME: 90ns LOW POWER CONSUMPTION Standby Current: 100µA Max 10,000 ERASE/PROGRAM CYCLES 12V PROGRAMMING VOLTAGE TYPICAL BYTE PROGRAMMING TIME 10µs (PRESTO F ALGORITHM) ELECTRICAL CHIP ERASE IN 1s RANGE INTEGRATED ERASE/PROGRAM STOP TIMER EXTENDED TEMPERATURE RANGES
32
1
PDIP32 (B)
PLCC32 (C)
Figure 1. Logic Diagram DESCRIPTION The M28F256 FLASH Memory Is a non-volatile memory which may be erased electrically at the chip level an d programmed byte-by-byte. It is organised as 32K bytes of 8 bits. It uses a command register architecture to select the operating modes and thus provides a simple microprocessor interface. The M28F256 FLASH Memory is suitable for applications where the memory has to be reprogrammed in t he equipment. The access time of 100ns makes the device suitable for use in high speed microprocessor systems.
VCC
VPP
15 A0-A14
8 DQ0-DQ7
W
M28F256
Table 1. Signal Names
A0 - A14 DQ0 - D Q7 E G W VPP VCC VSS Address Inputs Data Inputs / Outputs Chip Enable Output Enable Write Enable Program Supply Supply Voltage Ground
E G
VSS
AI00688B
March 1996
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M28F256
Figure 2A. DIP Pin Connections
VPP NC NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 M28F256 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC W NC A14 A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
Figure 2B. LCC Pin Connections
A 12 NC NC VPP VCC W NC 1 32 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 A14 A13 A8 A9 A11 G A10 E DQ7 9 M28F256 25 17 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6
AI00690
AI00689
Warning: NC = Not Connected
Warning: NC = Not Connected
Table 2. Absolute Maximum Ratings
Symbol TA TSTG VIO VC C VA9 VPP Parameter Am bient Operating Temperature Storage Temperature Input or Output Voltages Supply Voltage A9 Voltage Program Supply Voltage, during Erase or Programming Value 40 to 125 65 to 150 0.6 to 7 0.6 to 7 0.6 to 13.5 0.6 to 14 Unit °C °C V V V V
Note: Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents.
DEVICE OPERATION The M28F256 FLASH Memory employs a technology similar to a 256K EPROM but adds t o the device functionality by providing e lectrical erasure and programming. These functions are managed by a command register. The functions that are addressed via the command register depend on the voltage applied to the VPP, program voltage,
input. When VPP is less than or equal to 6.5V, the command register is disabled and M28F256 functions as a read only memory providing operating modes similar to an EPROM (Read, Output Disable, Electronic Signature Read a nd Standby ). When VPP is raised to 12V the command register is enabled and this provides, in addition, Erase and Program operations.
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M28F256
Table 3. Operations
VPP Read Only VPPL
(1)
Operation Read Output Disable Standby Electronic Signature
E VIL VIL VIH VIL VIL VIL VIL VIH
G VI L VIH X VI L VI L VIH VIH X
W VI H VI H X VI H VI H VIL Pulse VI H X
A9 A9 X X VID A9 A9 X X
DQ0 - D Q7 Data Output Hi-Z Hi-Z Codes Data Output Data Input Hi-Z Hi-Z
Read/Write
(2)
VPPH
Read Write Output Disable Standby
Notes: 1. X = VIL or VIH 2. Refer also to the Command Table
Table 4. Electronic Signature
Identifier Manufacturer's Code Device Code A0 VIL VIH DQ7 0 1 D Q6 0 0 DQ5 1 1 DQ4 0 0 DQ3 0 1 DQ2 0 0 DQ1 0 0 DQ0 0 0 Hex Data 20h 0A8h
READ ONLY MODES, VPP 6.5V For all Read Only Modes, except Standby Mode, the Write Enable input W should be High. In the Standb y Mode this input is 'don't care'. Read Mode. The M28F256 has two enable inputs, E and G, both o f which must be Low in order to output data from the memory. The Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data on to the output, indepen dant of the device selection. Standby Mode. In the Standb y Mode the maximum supply current is reduced to 100µA. The device is placed in the Standb y Mode by a pplying a High to the Chip Enable (E) input. When in the Standb y Mode the outputs are in a high impedanc e state, independan t of the Output Enable (G) input. Output Disable Mode. When the Output Enable (G) is High the outputs are in a high impedance state.
Electronic Signature Mode. This mode allows the read out of two binary codes from the device which identify the manufacturer and device t ype. This mode is intended f or use by programming equipment to automatically select the correct erase and programming algorithms. The Electronic Signature Mode is active when a high voltage (11.5V to 13V) is applied to address line A9 with E and G Low. With A0 Low the output data is the manufacturer code, when A0 is High the output is the device type code. All other address lines should be maintained Low while reading the codes. The electronic signature may also be accessed in Read/Write modes. READ/WRITE MODES, 11.4V VP P 12.6V When VPP is High both read and write operations may be performed. These are defined by the contents of an internal command register. Commands may be written to this register to set-up and execute, Erase, Erase Verify, Program, Program Verify and Reset modes. Each of these modes needs 2
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M28F256
Table 5. Commands (1)
Command Read Electronic Signature Setup Erase/ Erase Erase Verify Setup Program/ Program Program Verify Reset
Note: 1. X = VIL or VIH
Cycles Operation 1 2 Write Write Write
1st C ycle A0-A14 X X X DQ0-DQ7 00h 90h 20h Write Read Read Operation
2nd Cycle A0-A14 D Q0-DQ7
0000h 0001h
20h 0A8h
2 2 2 2 2
X X
20h Data Output
Write Write
A0-A14 X
0A0h 40h
Read
Write Write Write X X 0C0h 0FFh Read Write
A0-A14 X X
Data Input Data Output 0FFh
READ/WRITE MODES (cont'd) cycles. Every mode starts with a write operation to set-up the command, this is followed by either read or write operation s. The device expects the first cycle to be a write operation and do es not c orrupt data at any location in memory. Read mode is set-up with one cycle only and may be followed by any number of read operations to output data. Electronic Signature Read mode is set-up with one cycle and followed by a read cycle to output the manufacturer or device codes. A write to the command register is made by bringing W Low while E is Low. The falling edge of W latches Addresses, while the rising edge latches Data, which are used for those commands that require address inputs, command input or provide data output. The supply voltage VCC a nd the program voltage VP P can be applied in any order. When the device is powered up or when VPP is 6.5V the contents of the command register default to 00h, thus automatically setting-up Read operations. In addition a specific command may be used to se t the command register to 00h for reading the memory.
The system designer may choose to provide a constant high VPP and use the register commands for all operation s, or to switch the VPP f rom low to high only when needing to erase or program the memory. All command register access is inhibited when VCC falls below the Erase/Write Lockout Voltage (VLKO) at 2.5V. If the device is deselected during Erasure, Programming o r Verification it will draw active supply currents until the operations are terminated. The device is protected against stress caused by long erase or program times. If the end of Erase or Programming operations are not terminated by a Verify cycle within a maximum time permitted, an internal stop timer automatically s tops the operation. The device remains in an inactive state, ready to start a Verify or Reset Mode operation. Read Mode. The Read Mode is the default at power up or may be set-up by writing 00h t o the command register. Subsequen t read operation s output data from the memory. The memory remains in the Read Mode until a new command is written to the command register.
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M28F256
AC MEASUREMENT CONDITIONS
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 10ns 0.45V to 2.4V 0.8V to 2V
Figure 4. AC Testing Load Circuit
1.3V
Note that Output Hi-Z is defined as the point where data is no longer driven.
1N914
3.3k
Figure 3. AC Testing Input Output Waveforms
2.4V
DEVICE UNDER TEST CL = 100pF
OUT
2.0V 0.8V CL includes JIG capacitance
AI00827
0.45V
AI00828
Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz )
Symbol CI N COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 12 Un it pF pF
Note: 1. Sampled only, not 100% tested
Electronic Signature Mode. In order to select the correct erase and programming algorithms for onboard programming, the manufacturer and devices code may be read directly. I t is not neccessary to apply a high voltage to A9 when using the command register. The Electronic Signature Mode is set-up by writing 90h to the command register. The following read cycle, with address inputs 0000h or 0001h, output the manufacturer or device t ype codes. The command is terminated by writing another valid command to the command register (for example Reset). Erase and Erase Verify Modes. The memory is erased by first Programming all bytes to 00h, the Erase command then erases them to 0FFh. The Erase Verify command is then used to read the memory byte-by-byte for a content o f 0FFh. The Erase Mode is set-up by writing 20h to the command register. The write cycle is then repeated to s tart the erase operation. Erasure starts on the rising edge of W during this second cycle. Erase is
followed by an Erase Verify which reads an addressed byte. Erase Verify Mode is set-up by writing 0A0h to the command register and at the same time supplying the address o f the byte to be verified. The rising edge of W during the set-up of the first Erase Verify Mode stops the Erase operation. The following read cycle is made with an internally generate d margin voltage applied; reading 0FFh indicates that all bits of the addressed byte are fully erased. The whole contents o f the memory are verified by repeating the Erase Verify Operation, first writing the set-up code 0A0h with the address o f the byte to be verified and then reading the byte content s in a second read cycle. As the Erase algorithm flow chart shows, when the data read during Erase Verify is not 0FFh, another Erase operation is performed and verification continues from the address of the last verified byte. The command is terminated by writing another valid command to the command register (for example Program or Reset).
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