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Part: 4910A
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Datasheet: Download 4910A datasheet File size : 220 kB
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INTEGRATED CIRCUITS
DATA SHEET
P32P4910A PRML Read Channel with PR4, 8/9 ENDEC, 4-Burst Servo
Product Specification 1996 May 29
Philips Semiconductors
Product specification
PRML Read Channel with PR4, 8/9 ENDEC, 4-Burst Servo
GENERAL DESCRIPTION
P32P4910A
The Philips Semiconductors P32P4910A is a high performance BiCMOS read channel IC that provides all of the functions needed to implement an entire Partial Response Class 4 (PR4) read channel for zoned recording hard disk drive systems with data rates from 42 to 125 Mbit/s or 33 to 100 Mbit/s. Functional blocks include AGC, programmable filter, adaptive transversal filter, Viterbi qualifier, 8,9 GCR ENDEC, data synchronizer, time base generator, and 4-burst servo. Programmable functions such as data rate, filter cutoff, filter boost, etc., are controlled by writing to the serial port registers so no external component changes are required to change zones. The part requires a single +5V power supply. The Philips Semiconductors P32P4910A utilizes an advanced BiCMOS process technology along with advanced circuit design techniques which result in high performance devices with low power consumption. FEATURES General: · Register programmable data rates from 42 to 125 Mbit/s or 33 to 100 Mbit/s · Sampled data read channel with Viterbi qualification · Programmable filter for PR4 equalization · Five tap transversal filter with adaptive PR4 equalization · 8/9 GCR ENDEC · Data Scrambler/Descrambler · Presettable Precoder State · Programmable write precompensation · Low operating power (0.925 W typical at 5V) · Register programmable power management (<5 mW power down mode) · 4-bit nibble and byte-wide bi-directional NRZ data interfaces · 8-bit Direct Write mode automatically configured for RCLK = VCO/8 · Serial interface port for access to internal program storage registers · Single power supply (5V ± 10%) · Small footprint, 100-lead LQFP package
1996 May 29
2
853-1829 16870
PPOL
TPA-
VRX
TPD-
TPC-
RDS/RDS
EQHOLD
TPA+
TPB+
TPB-
TPD+
TPC+
TPE
VRDT
SFWR
LOWZ
VIA+ OD+ ODON+ DC OFFSET LEVEL OR HYSTERESIS PULSE QUAL CHANQUAL EN LOWZ VITERBI MUX DESCRAMBLER DSCLK 8,9 (0,4/4) SCRAMBLER ENCODER CODE WORD BOUNDRY DETECTOR CWBD DETECTOR 5-TAP EQUALIZER 2 -ADAPTIVE 2-PROG SSBYP DSCLK ASYMM FACTOR From Level Qual COUNTER SERVO DAC FULL WAVE WAVE RECTIFIER VCO SYNC PATTERN GEN TBGOUT HOLD FASTREC LOWZ SQUELCH x2 UFDC x2 VREF x2 PHASE/ FREQ DETECTOR x2 DAMPING CONTROL SERVO LEAKAGE + DECISION SFWR DATA SYNCHRONIZER RECTIFIER MUX PRECODER FULL PARALLEL TO SERIAL SYNC FIELD SFC AUTOMATIC TRAINING & SYNC BYTE GENERATOR SERIAL TO PARALLEL 9,8 (0,4/4) DECODER SFC To SFC PARITY GEN/CHK CN DP DN CANCEL ON-
CP
FASTREC
UFDC
A
B
C
D
FREF
RR
VPA1
VPD1
RESET
VPD2
VPA2
VPA3
PDWN
DGND1
AGND2
DGND2
FLTR1+
FLTR1-
FLTR2+
STROBE
Product specification
P32P4910A
Philips Semiconductors P32P4910A SSI 32P4910 BLOCK DIAGRAM
MAXREF
FLTR2-
AGND1
AGND3
1996 May 29
TPD MUX TPE MUX TEST POINT MUX TPC MUX SBD DUAL "OR" TYPE SYNC BYTE DETECTOR PERR NRZP PARALLEL INTERFACE NRZ0-7 WCLK NIBBLE INTERFACE RCLK
BLOCK DIAGRAM
Philips Semiconductors
VIA-
A LOWZ GC AMP
PROGRAMMABLE 7th-ORDER LOW-PASS
FILTER ASYMMETRIC 0'S
SQUELCH
BYPS
SG
VMIN
BYP
HOLD
PRML Read Channel with PR4, 8/9 ENDEC, 4-Burst Servo
HOLD
AGCRST
VCC
UFDC
SFC
DWI DWI
3
DIRECTED PHASE DETECTOR TBGOUT TIME BASE GENERATOR DECODE LOGIC 3.2 V REF 1/12 1/(N+1) 1/(M+1) PHASE/ FREQ DETECTOR CHARGE PUMP VCO
SAMPLED AGC
CONV AGC
CHARGE PUMP
CHARGE PUMP
MUX
WRITE PRECOMP
MUX
WRITE T FLIP-FLOP
WD WD
LOWZ
DWR
FASTREC
AGC
WRDEL
LZTO
CONTROL LOGIC
AGCDEL
FDTO
CWBD CHARGE PUMP VCO DSCLK TBGOUT RCLK CLOCK GEN RCLK RCLK
VRC
VREF
SDEN
ATO TEST MUX ATO
SCLK
CHANQUAL ASYMM FACTOR MAXREF/2 DACs
SDATA
SERIAL PORT & CONTROL REGISTERS
SG
POWER DOWN CONTROL
CONTROL
RG
LOGIC
WG/WG
Philips Semiconductors
Product specification
PRML Read Channel with PR4, 8/9 ENDEC, 4-Burst Servo
Automatic Gain Control: · Dual mode AGC, analog during acquisition, sampled during data reads · Separate AGC level storage pins for data and servo · Dual rate attack and decay charge pump for rapid AGC recovery (analog) · Programmable, symmetric, charge pump currents for data reads (sampled) · Charge pump currents track programmable data rate during data reads (sampled) · Low drift AGC hold circuitry · Low-Z circuitry at AGC input provides for rapid external coupling capacitor recovery · AGC Amplifier squelch during Low-Z · Wide bandwidth, precision full-wave rectifier · Programmable AGC controls Separate external input pins for AGC hold, fast recovery, and Low-Z control or
P32P4910A
Internal Low-Z and fast decay timing for rapid transient recovery and AGC acquisition. Timing set with external resistors (2). Ultra fast decay current set with external resistor. AGC input impedance vs LOWZ = 5:1. · 2-bit DAC to control AGC voltage in servo mode between 1.1 and 1.4 V Filter/Equalizer: · Programmable, 7-pole, continuous time filter provides: Channel filter and pulse slimming equalization for equalization to PR4 Programmable cutoff frequency from 4 to 34 MHz Programmable boost /equalization of 0 to 13 dB Programmable "zeros" equalization provides time asymmetry compensation ±0.5 ns group delay variation from 0.3c to c, with c = 34 MHz Minimizes size and power Low-Z switch at filter output for fast offset recovery No external coupling capacitors required DC offset compensation provided at filter output Five tap transversal filter for fine equalization to PR4 Self adapting inner taps (symmetric) Programmable outer taps (symmetric, 4-bits) Equalization hold input "Zeros" channel quality output Amplitude asymmetry factor output Pulse Qualification: · Sampled Viterbi qualification of signal equalized to PR4 · Register programmable window or hysteresis pulse qualifier for servo reads · Selectable RDS pulse width and polarity for servo gray code reads
1996 May 29
4
Philips Semiconductors
Product specification
PRML Read Channel with PR4, 8/9 ENDEC, 4-Burst Servo
Time Base Generator: · Less than 1% frequency resolution · Up to 141 MHz frequency output · Independent M and N divide-by registers · No active external components required Data Separator: · Fully integrated data separator includes data synchronizer and 8,9 GCR ENDEC · Register programmable to 125 Mbit/s operation · Fast Acquisition, sampled data phase lock loop · Decision directed clock recovery from data samples · Adaptive clock recovery thresholds · Programmable damping ratio for data synchronizer PLL is constant for all data rates · Data scrambler/descrambler to reduce fixed pattern effects · 4-bit nibble and byte-wide NRZ data interfaces · Time base tracking, programmable write precompensation · Differential PECL write data output · Integrated sync byte detection, single byte or dual ("or" type) · Semi-auto training and sync byte generation available for single sync byte operation · Surface defect scan mode Servo: · 4-burst servo capture with A, B, C, D outputs · Internal hold capacitors · "Soft Landing" charge pump architecture · Separate, automatically selected, registers for servo c, boost, and threshold · Programmable charge pump current · Wide bandwidth, precision full-wave rectifier · Programmable selection of normal or differentiated filter output to servo capture block · Programmable AGC gain in servo mode (2-bits) · Full wave rectifier observation point
P32P4910A
1996 May 29
5
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