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Details, datasheet, quote on part number:4910B
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Datasheet text preview:
INTEGRATED CIRCUITS
P32P4910B PRML Read Channel with PR4, 8/9 ENDEC, 4-Burst Servo
Product specification 1997 July 15
Philips Semiconductors
Philips Semiconductors
Product specification
PRML Read Channel with PR4, 8/9 ENDEC, 4-Burst Servo
P32P4910B
GENERAL DESCRIPTION
The Philips Semiconductors P32P4910B is a high performance BiCMOS read channel IC that provides all of the functions needed to implement an entire Partial Response Class 4 (PR4) read channel for zoned recording hard disk drive systems with data rates from 42 to 125 Mbit/s or 33 to 100 Mbit/s. Functional blocks include AGC, programmable filter, adaptive transversal filter, Viterbi qualifier, 8,9 GCR ENDEC, data synchronizer, time base generator, and 4-burst servo. Programmable functions such as data rate, filter cutoff, filter boost, etc., are controlled by writing to the serial port registers so no external component changes are required to change zones. The part requires a single +5V power supply. The Philips Semiconductors P32P4910B utilizes an advanced BiCMOS process technology along with advanced circuit design techniques which result in high performance devices with low power consumption.
Automatic Gain Control:
reads
· Dual mode AGC, analog during acquisition, sampled during data · Separate AGC level storage pins for data and servo · Dual rate attack and decay charge pump for rapid AGC recovery
(analog)
· Programmable, symmetric, charge pump currents for data reads
(sampled)
· Charge pump currents track programmable data rate during data
reads (sampled)
· Low drift AGC hold circuitry · Low-Z circuitry at AGC input provides for rapid external coupling
capacitor recovery
FEATURES General:
· AGC Amplifier squelch during Low-Z · Wide bandwidth, precision full-wave rectifier · Programmable AGC controls
Separate external input pins for AGC hold, fast recovery, and Low-Z control or Internal Low-Z and fast decay timing for rapid transient recovery and AGC acquisition. Timing set with external resistors (2). Ultra fast decay current set with external resistor. AGC input impedance vs LOWZ = 5:1.
· Register programmable data rates from 42 to 125 Mbit/s or
33 to 100 Mbit/s
· Sampled data read channel with Viterbi qualification · Programmable filter for PR4 equalization · Five tap transversal filter with adaptive PR4 equalization · 8/9 GCR ENDEC · Data Scrambler/Descrambler · Presettable precoder state · Programmable write precompensation · Low operating power (0.85 W typical at 5V) · Register programmable power management
(<5 mW power down mode)
· 2-bit DAC to control AGC voltage in servo mode between 1.1
and 1.4 V
Filter/Equalizer:
· Programmable, 7-pole, continuous time filter provides:
Channel filter and pulse slimming equalization for equalization to PR4 Programmable cutoff frequency from 4 to 34 MHz Programmable boost /equalization of 0 to 13 dB Programmable "zeros" equalization provides time asymmetry compensation ±0.5 ns group delay variation from 0.3c to c, with c = 34 MHz Minimizes size and power Low-Z switch at filter output for fast offset recovery No external coupling capacitors required DC offset compensation provided at filter output Five tap transversal filter for fine equalization to PR4 Self adapting inner taps (symmetric) Programmable outer taps (symmetric, 4-bits) Equalization hold input "Zeros" channel quality output Amplitude asymmetry factor output
· 4-bit nibble and byte-wide bi-directional NRZ data interfaces · I/O Mapping and In circuit test · 8-bit Direct Write mode automatically configured for
RCLK = VCO/8
· Thermal asperity detection and suppression · Bi-directional serial interface port for access to internal program
storage registers (read and write capability)
· Single power supply (5V ± 10%) · Small footprint, 100-lead LQFP package
1997 JuL 15
2
853-1952 18177
Philips Semiconductors
Product specification
PRML Read Channel with PR4, 8/9 ENDEC, 4-Burst Servo
P32P4910B
Pulse Qualification:
· Sampled Viterbi qualification of signal equalized to PR4 · Register programmable window or hysteresis pulse qualifier for
servo reads
· Semi-auto training and sync byte generation available for single
sync byte operation
· Surface defect scan mode
Servo:
· Selectable RDS pulse width and polarity for servo gray code reads
Time Base Generator:
· Less than 1% frequency resolution · Up to 141 MHz frequency output · Independent M and N divide-by registers · No active external components required
Data Separator:
8,9 GCR ENDEC
· 4-burst servo capture with A, B, C, D outputs · Internal hold capacitors · "Soft Landing" charge pump architecture · Separate, automatically selected, registers for servo c, boost,
and threshold
· Fully integrated data separator includes data synchronizer and · Register programmable to 125 Mbit/s operation · Fast Acquisition, sampled data phase lock loop · Decision directed clock recovery from data samples · Adaptive clock recovery thresholds · Programmable damping ratio for data synchronizer PLL is
constant for all data rates
· Programmable charge pump current · Wide bandwidth, precision full-wave rectifier · Programmable selection of normal or differentiated filter output to
servo capture block
· Programmable AGC gain in servo mode (2-bits) · Full wave rectifier observation point
Thermal Asperity:
time filter
· Internal TA detector that monitors DP/DN output of continuous · Hi-Y input modulation to rapidly attenuate offset due to TA · AGC and PLL hold that may be triggered by TA event · EFLAG output is dynamically generated to flag TA corrupted NRZ
data
· Data scrambler/descrambler to reduce fixed pattern effects · 4-bit nibble and byte-wide NRZ data interfaces · Time base tracking, programmable write precompensation · Differential PECL write data output · Integrated sync byte detection, single byte or dual ("or" type)
· TAD input pin allows use of an external TA event detector
1997 JuL 15
3
1997 JuL 15
DN CN VRDT RDS ON+ PPOL TPB+ TPB TPA+ TPA DP CP LEVEL TYPE PULSE QUAL To SFC SYNC BYTE DETECTOR TEST POINY MUX SAMPLE & HOLD VITERBI DETECTOR DESCRAMBLER DSCLK SCRAMBLER MUX 9,8 DECODER PLL TAD DSCLK SYNC FIELD COUNTER RCLK DWI DWI PRECODER MUX WD WRITE PRECOMP MUX WRITE FLIP-FLOP MUX WD VCO SYNC PATTERN GEN TBGOUT SFWR DWR MUX PARALLEL TO SERIAL CWBD 9,8 ENCODER 3TAP ADAPTIVE EQUALIZER PARALLEL TO SERIAL PARALLEL INTERFACE NRZ07 WCLK DUAL BIT INTERFACE DB0DB1 CODE WORD BOUNDRY DETECTOR FULLWAVE RECTIFIER FROM LEVEL QUAL + x3 x3 DATA SYNCHRONIZER DECISION DIRECTED PHASE DETECTOR CWBD DSCLK CHARGE PUMP PHASE/ FREQ DETECTOR DAMPING CONTROL ATO DAC TEST MUX TBGOUT ATRN VCO TBGOUT RCLK CLOCK GEN RCLK NCLK RCLK x3 x3 TIME BASE GENERATOR DECODE LOGIC 3.2V REF 1/12 1/(M+1) 1/(N+1) POWER DOWN CONTROL PHASE/ FREQ DETECTOR CHARGE PUMP VCO RR VPA1 VPA2 VPA3 FREF VPD1 VPD2 PDWN A B C D AGND1 AGND2 AGND3 DGND1 DGND2 FLTR1 FLTR2 FLTR1+ FLTR2+
Philips Semiconductors
OD+
OD
ON
BLOCK DIAGRAM
VRX
VIA+
AGC AMP
VIA
PROGRAMMABLE 7TH ORDER LOW PASS FILTER
BYPS
BYP
TA
HOLD
AGC
PRML Read Channel with PR4, 8/9 ENDEC, 4-Burst Servo
VRC
VREF
SAMPLED AGC CHARGE PUMP
CONV AGC CHARGE PUMP
LOWZ
4
RESET STROBE MAXREF
FASTREC
AGC CONTROL LOGIC
VREF
SDEN
SCLK
SDATA
SERIAL PORT & CONTROL REGISTERS
SG
RG
CONTROL LOGIC
WG
P32P4910B
Product specification
Philips Semiconductors P32P4910B
SM00171
Philips Semiconductors
Product specification
PRML Read Channel with PR4, 8/9 ENDEC, 4-Burst Servo
P32P4910B
P32P4910BP Pinout 100 LQFP
PPOL/EFLAG
RDS/RDS/TAD
TPC
TPC+
TPD
VIA
BURST D
BURST C
BURST A
BURST B
AGCRST
AGCDEL
WRDEL
TPD+
VIA+
VRX
VNA
VPA
TPE
NC
NC
SG
NC
NC
NC NC BYPD BYPS HOLD LOWZ FASTREC VRDT SCLK SDATA SDEN VPF FREF VNF VPT FLTR1+ FLTR1 VNT DWI DWI WD WD NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
NC 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
TAD EFLAG VRC RR MAXREF RESET STROBE VPS VNS TPA+ TPA TPB+ TPB VPS ATO EQHOLD VNS VPP FLTR2+ FLTR2 VNP VNC NC NC NC
51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 WG/WG PERR PDWN WCLK NRZ0 NRZ1 NRZ2 NRZ3 NRZ4 NRZ5 NRZ6 NRZ7 NRZP RCLK DWR SBD VND VPD VPC RG NC NC NC NC NC
SM00172
1997 JuL 15
5
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