Details, datasheet, quote on part number: 4910B
DatasheetDownload 4910B datasheet


Features, Applications

P32P4910B PRML Read Channel with PR4, 8/9 ENDEC, 4-Burst Servo
PRML Read Channel with PR4, 8/9 ENDEC, 4-Burst Servo

The Philips Semiconductors is a high performance BiCMOS read channel IC that provides all of the functions needed to implement an entire Partial Response Class 4 (PR4) read channel for zoned recording hard disk drive systems with data rates from to 125 Mbit/s to 100 Mbit/s. Functional blocks include AGC, programmable filter, adaptive transversal filter, Viterbi qualifier, 8,9 GCR ENDEC, data synchronizer, time base generator, and 4-burst servo. Programmable functions such as data rate, filter cutoff, filter boost, etc., are controlled by writing to the serial port registers so no external component changes are required to change zones. The part requires a single +5V power supply. The Philips Semiconductors P32P4910B utilizes an advanced BiCMOS process technology along with advanced circuit design techniques which result in high performance devices with low power consumption.

Dual mode AGC, analog during acquisition, sampled during data Separate AGC level storage pins for data and servo Dual rate attack and decay charge pump for rapid AGC recovery

Programmable, symmetric, charge pump currents for data reads
Charge pump currents track programmable data rate during data
Low drift AGC hold circuitry Low-Z circuitry at AGC input provides for rapid external coupling

AGC Amplifier squelch during Low-Z Wide bandwidth, precision full-wave rectifier Programmable AGC controls

Separate external input pins for AGC hold, fast recovery, and Low-Z control or Internal Low-Z and fast decay timing for rapid transient recovery and AGC acquisition. Timing set with external resistors (2). Ultra fast decay current set with external resistor. AGC input impedance vs LOWZ = 5:1.

Register programmable data rates from to 125 Mbit/s or

Sampled data read channel with Viterbi qualification Programmable filter for PR4 equalization Five tap transversal filter with adaptive PR4 equalization 8/9 GCR ENDEC Data Scrambler/Descrambler Presettable precoder state Programmable write precompensation Low operating power (0.85 W typical at 5V) Register programmable power management

Channel filter and pulse slimming equalization for equalization PR4 Programmable cutoff frequency from to 34 MHz Programmable boost /equalization dB Programmable "zeros" equalization provides time asymmetry compensation 0.5 ns group delay variation from to c, with = 34 MHz Minimizes size and power Low-Z switch at filter output for fast offset recovery No external coupling capacitors required DC offset compensation provided at filter output Five tap transversal filter for fine equalization PR4 Self adapting inner taps (symmetric) Programmable outer taps (symmetric, 4-bits) Equalization hold input "Zeros" channel quality output Amplitude asymmetry factor output

4-bit nibble and byte-wide bi-directional NRZ data interfaces I/O Mapping and In circuit test 8-bit Direct Write mode automatically configured for

Thermal asperity detection and suppression Bi-directional serial interface port for access to internal program

Single power supply 10%) Small footprint, 100-lead LQFP package

Sampled Viterbi qualification of signal equalized to PR4 Register programmable window or hysteresis pulse qualifier for

Semi-auto training and sync byte generation available for single
Selectable RDS pulse width and polarity for servo gray code reads

Less than 1% frequency resolution to 141 MHz frequency output Independent M and N divide-by registers No active external components required

4-burst servo capture with C, D outputs Internal hold capacitors "Soft Landing" charge pump architecture Separate, automatically selected, registers for servo c, boost,

Fully integrated data separator includes data synchronizer and Register programmable to 125 Mbit/s operation Fast Acquisition, sampled data phase lock loop Decision directed clock recovery from data samples Adaptive clock recovery thresholds Programmable damping ratio for data synchronizer PLL is

Programmable charge pump current Wide bandwidth, precision full-wave rectifier Programmable selection of normal or differentiated filter output to

Programmable AGC gain in servo mode (2-bits) Full wave rectifier observation point

Internal TA detector that monitors DP/DN output of continuous Hi-Y input modulation to rapidly attenuate offset due to TA AGC and PLL hold that may be triggered by TA event EFLAG output is dynamically generated to flag TA corrupted NRZ

Data scrambler/descrambler to reduce fixed pattern effects 4-bit nibble and byte-wide NRZ data interfaces Time base tracking, programmable write precompensation Differential PECL write data output Integrated sync byte detection, single byte or dual ("or" type)


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