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Part: 59C11I/P
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Datasheet: Download 59C11I/P datasheet File size : 136 kB
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59C11
1K 5.0V Microwire® Serial EEPROM
FEATURES
· Low power CMOS technology · Pin selectable memory organization - 128 x 8 or 64 x 16 bit organization · Single 5V only operation · Self timed WRITE, ERAL and WRAL cycles · Automatic erase before WRITE · RDY/BSY status information during WRITE · Power on/off data protection circuitry · 1,000,000 ERASE/WRITE cycles guaranteed · Data Retention > 200 Years · 8-pin DIP or SOIC package · Temperature ranges supported - Commercial (C): 0°C to +70°C - Industrial (I): -40°C to +85°C - Automotive (E): -40°C to +125°C
PACKAGE TYPES
DIP
CCS LK D DI O 2 1 7 8 R V CC ODY/BSY V RG
SS
59C 11
3 4
6 5
SOIC
2 1 7 8
CCS LK D DI O
R V CC ODY/BSY V RG
SS
59C11
3 4
6 5
DESCRIPTION
The Microchip Technology Inc. 59C11 is a 1K bit Electrically Erasable PROM. The device is configured as 128 x 8 or 64 x 16, selectable externally by means of the control pin ORG. Advanced CMOS technology makes this device ideal for low power nonvolatile memory applications. The 59C11 is available in the standard 8-pin DIP and a surface mount SOIC package.
BLOCK DIAGRAM
VCC VSS
ORG
MEMORY ARRAY 128 x 8 or 64 x 16
ADDRESS DECODER
DATA REGISTER DI MODE DECODE LOGIC
OUTPUT BUFFER
DO
CS
RDY/BSY
CLK
CLOCK GENERATOR
Microwire is a registered trademark of National Semiconductor Incorporated.
© 1996 Microchip Technology Inc.
DS20040J-page 1
This document was created with FrameMaker 4 0 4
59C11
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
TABLE 1-1:
Name CS CLK DI DO VSS ORG RDY/BSY VCC
PIN FUNCTION TABLE
Function Chip Select Serial Clock Data In Data Out Ground Memory Array Organization Ready/Busy Status +5V Power SUpply
VCC..7.0V All inputs and outputs w.r.t. VSS ...... -0.6V to VCC +1.0V Storage temperature .......... -65°C to +150°C Ambient temperature with power applied...... -65°C to +125°C Soldering temperature of leads (10 seconds) .... +300°C ESD protection on all pins......4 kV
*Notice: Stresses above those listed under "Maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 1-2:
DC CHARACTERISTICS
Commercial (C): Industrial (I): Automotive (E): Symbol Min Max Units Tamb Tamb Tamb = 0°C to 70°C = -40°C to +85°C = -40°C to 125°C Conditions
VCC = +5.0V (±10%)
Parameter
VCC detector threshold VTH 2.8 4.5 V High level input voltage VIH 2.0 Vcc+1 V Low level input voltage VIL -0.3 0.8 V High level output voltage VOH 2.4 -- V Low level output voltage VOL -- 0.4 V -- 10 µA Input leakage current ILI Output leakage current ILO -- 10 µA Pin capacitance CIN, -- 7 pF (all inputs/outputs) COUT Operating current (all modes) ICC write -- 4 mA -- 100 µA Standby current ICCS Note 1: Internal resister pull-up at Pin 6. Active output at Pin 7. 2: This parameter is periodically sampled and not 100% tested.
IOH = -400 µA IOL = 3.2 mA VIN = 0V to VCC (Note 1) VOUT = 0V to VCC (Note 1) VIN/VOUT = 0V (Note 2) Tamb = 25°C, f = 1 MHz FCLK = 1 MHz, VCC = 5.5V CS = 0V, VCC = 5.5V
FIGURE 1-1:
SYNCHRONOUS DATA TIMING
TCKH TCKL TCSH V IH
CLK TDIH TDIS DI VALID TDIH TDIS V IH VALID V IL TCSL CS TCSS TPD VALID V IH V IL TPD DO TCZ VALID HIGH Z V IH/ V OH V IL/ V OL V IL
DS20040J-page 2
© 1996 Microchip Technology Inc.
59C11
TABLE 1-3: AC CHARACTERISTICS
Parameter Clock frequency Clock high time Clock low time Chip select setup time Chip select hold time Chip select low time Data input setup time Data input hold time Data output delay time Data output disable time (from CS = low) Data output disable time (from last clock) RDY/BSY delay time Program cycle time (Auto Erase and Write) Symbol FCLK TCKH TCKL TCSS TCSH TCS TDIS TDIH TPD TCZ TDDZ TRBD Twc 500 500 50 0 100 100 100 -- 0 0 -- -- Min Max 1 -- -- -- -- -- -- -- 400 100 400 400 1 15 -- Units MHz ns ns ns ns ns ns ns ns ns ns ns ms ms cycles for 8-bit mode for ERAL and WRAL in 8/16-bit modes 25°C, Vcc = 5.0V, Block Mode (Note 1) CL = 100 pF CL = 100 pF CL = 100 pF Conditions
Endurance
--
1M
Note 1: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website.
TABLE 1-4:
INSTRUCTION SET
6 X 16 MODE, ORG = 1
Instruction READ WRITE EWEN EWDS ERAL WRAL
Start Bit 1 1 1 1 1 1
Opcode 10XX X1XX 0011 0000 0010 0001
Address A5 A4 A3 A2 A1 A0 A5 A4 A3 A2 A1 A0 X X X X X X X X X X X X X X X X X X X X X X X X
Data In -- D15-D0 -- -- -- D15-D0
Data Out D15-D0 High-Z High-Z High-Z High-Z High-Z
Number of Req. CLK CYcles 27 27 11 11 11 27
128 X 8 MODE, ORG = 0 Instruction READ WRITE EWEN EWDS ERAL WRAL Start Bit 1 1 1 1 1 1 Opcode 10XX X1XX 0011 0000 0010 0001 Address A6 A5 A4 A3 A2 A1 A0 A6 A5 A4 A3 A2 A1 A0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X Data In -- D7-D0 -- -- -- D7-D0 Data Out D7-D0 High-Z High-Z High-Z High-Z High-Z Number of Req. CLK CYcles 20 20 12 12 12 20
© 1996 Microchip Technology Inc.
DS20040J-page 3
59C11
2.0
2.1
FUNCTIONAL DESCRIPTION
START Condition
2.4
READ Mode
The START bit is detected by the device if CS and DI are both High with respect to the positive edge of CLK for the first time. Before a START condition is detected, CS, CLK, and DI may change in any combination (except to that of a START condition) without resulting in any device operation (READ, WRITE, EWEN, EWDS, ERAL, and WRAL). As soon as CS is HIGH, the device is no longer in the standby mode. An instruction following a START condition will only be executed if the required amount of opcode, address and data bits for any particular instruction is clocked in. After execution of an instruction (i.e. clock in or out of the last required address or data bit) CLK and DI become don't care bits until a new start condition is detected. Note: CS must go LOW between consecutive instructions.
The READ instruction outputs the serial data of the addressed memory location on the DO pin. A dummy bit (logical 0) precedes the 8- or 16-bit output string. The output data changes during the high state of the system clock (CLK). The dummy bit is output TPD after the positive edge of CLK, which was used to clock in the last address bit (A0). Therefore, care must be taken if DI and DO are connected together as a bus contention will occur for one clock cycle if A0 is a one. DO will go into HIGH-Z mode with the positive edge of the next CLK cycle. This follows the output of the last data bit D0 or the negative edge of CS, whichever occurs first. D0 remains stable between CLK cycles for an unlimited time as long as CS stays HIGH. The most significant data bit (D15 or D7) is always output first, followed by the lower significant bits (D14 - D0 or D6 - D0).
2.5
WRITE
2.2
DI/DO Pins
It is possible to connect the Data In and Data Out pins together. However, with this configuration it is possible for a "bus conflict" to occur during the "dummy zero" that precedes the READ operation, if A0 is a logic high level. Under such a condition the voltage level seen at Data Out is undefined and will depend upon the relative impedances of Data Out and the signal source driving A0. The higher the current sourcing capability of A0, the higher the voltage at the Data Out pin.
The WRITE instruction is followed by 8 or 16 bits of data which are written into the specified address. The most significant data bit (D15 or D7) has to be clocked in first followed by the lower significant data bits (D14 D0 or D6 D0). If a WRITE instruction is recognized by the device and all data bits have been clocked in, the device performs an automatic erase cycle on the specified address before the data are written. The WRITE cycle is completely self timed and commences automatically after the rising edge of the CLK signal for the last data bit (D0). The WRITE cycle takes 1 ms maximum for 8-bit mode and 2 ms maximum for 16-bit mode.
2.3
Data Protection
2.6
During power-up, all modes of operation are inhibited until VCC has reached a level of 2.8 V. During powerdown, the source data protection circuitry acts to inhibit all modes when VCC has fallen below 2.8 V. The EWEN and EWDS commands give additional protection against accidentally programming during normal operation. After power-up, the device is automatically in the EWDS mode. Therefore, EWEN instruction must be performed before any WRITE, ERAL or WRAL instruction can be executed. After programming is completed, the EWDS instruction offers added protection against unintended data changes.
Erase/Write Enable and Disable (EWEN, EWDS)
The device is automatically in the ERASE/WRITE Disable mode (EWDS) after power-up. Therefore, EWEN instruction has to be performed before any WRITE, ERAL, or WRAL instruction is executed by the device. For added data protection, the device should be put in the ERASE/WRITE Disable mode (EWDS) after programming operations are completed.
2.7
ERASE All (ERAL)
The entire chip will be erased to logical "1s" if this instruction is received by the device and it is in the EWEN mode. The ERAL cycle is completely self-timed and commences after the rising edge of the CLK signal for the last dummy address bit. ERAL takes 15 ms maximum.
DS20040J-page 4
© 1996 Microchip Technology Inc.
59C11
2.8 WRITE All (WRAL)
The entire chip will be written with the data specified in that command. The WRAL cycle is completely selftimed and commences after the last data bit (D0) has been clocked in. WRAL takes 15 ms maximum.
Note:
The WRAL does not include an automatic ERASE cycle for the chip. Therefore, the WRAL instruction must be preceded by an ERAL instruction and the chip must be in the EWEN status in both cases. The WRAL instruction is used for testing and/or device initialization.
FIGURE 2-1:
CLK
READ MODE
CS SB DI 1 DO NOTE: ORGANIZATION 128 x 8 64 x 16 AN A6 A5 DN D7 D15 1 0 X X X TPD HIGH - Z 0 DN D0 X OPCODE AN A0
T CSL
T DDZ
NEW INSTRUCTION OR STANDBY (CS = 0)
FIGURE 2-2:
CLK
WRITE MODE
TCSL CS SB DI 1 DO RDY/BSY X 1 X HIGH - Z TRBD X X X X X OPCODE AN A0 DN D0
NOTE:
ORGANIZATION 128 x 8 64 x 16
AN A6 A5
DN D7 D15
TWC NEW INSTRUCTION OR STANDBY (CS = 0)
© 1996 Microchip Technology Inc.
DS20040J-page 5
Others parts begin by 59
59-1 59-2 59-3 59-4 59-5 59-6 59-7 59-8 59-9 59-10 59-11 59-12 59-13 59-14 59-15 59-16 59-17 59-18 59-19 59-20 59-21 59-22 59-23 59-24 59-25
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