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Part: 74ALS175D
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INTEGRATED CIRCUITS
74ALS175 Quad D flipflop
Product specification IC05 Data Handbook 1991 Feb 08
Philips Semiconductors
Philips Semiconductors
Product specification
Quad D flip-flop
74ALS175
FEATURES
· Four edge-triggered D flip-flops · Buffered common clock · Buffered asynchronous master reset · True and complementary outputs
DESCRIPTION
The 74ALS175 is a quad, edge-triggered D-type flip-flops with individual D inputs and both Q and Q outputs. The common buffered clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop's Q output. All Q outputs will be forced Low independent of clock or data inputs by a Low voltage level on the MR input. The device is useful for applications where both true and complement outputs are required, and the clock and master reset are common to all storage elements. TYPICAL SUPPLY CURRENT (TOTAL) 7mA
PIN CONFIGURATION
MR 1 16 VCC 15 Q3 14 Q3 13 D3 12 D2 11 Q2 10 Q2 9 CP
Q0 2 Q0 3 D0 4 D1 5 Q1 6 Q1 7 GND 8
SF00718
ORDERING INFORMATION
ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C 74ALS175N 74ALS175D DRAWING NUMBER
TYPE 74ALS175
TYPICAL fMAX 70MHz
16-pin plastic DIP 16-pin plastic SO
SOT38-4 SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS D0 D3 CP MR Q0 Q3 Q0 Q3 Data inputs Clock Pulse input (active rising edge) Master Reset input (active-Low) True outputs Complementary outputs DESCRIPTION 74ALS (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 20/80 20/80 LOAD VALUE HIGH/LOW 20µA/0.1mA 20µA/0.1mA 20µA/0.1mA 0.4mA/8mA 0.4mA/8mA
NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
LOGIC SYMBOL
4 5 12 13
IEC/IEEE SYMBOL
1 9 R C1 2 4 1D 3 7 5 6 Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 12 10 11 15 13 14
D0 D1 D2 D3 9 1 CP MR
2 VCC = Pin 16 GND = Pin 8
3
7
6
10 11 15 14
SF00719
SF00720
1991 Feb 08
2
8531024 01670
Philips Semiconductors
Product specification
Quad D flip-flop
74ALS175
LOGIC DIAGRAM
D0 4 CP 9 D1 5 D2 12 D3 13
D
Q
D
Q
D
Q
D
Q
CP RD MR VCC = Pin 16 GND = Pin 8 1 3 2 Q0 Q0
CP RD
CP RD
CP Q RD
6 Q1
7 Q1
11 Q2 Q2
10 Q3
14
15 Q3
SF00721
FUNCTION TABLE
INPUTS MR L H H CP X D X h I Qn L H L OUTPUTS Qn H L H OPERATING MODE Reset (clear) Load "1" Load "0"
NOTES: H = High-voltage level h = High state must be present one setup time before the Low-to-High clock transition L = Low-voltage level l = Low state must be present one setup time before the Low-to-High clock transition X = Don't care = Low-to-High clock transition
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Operating free-air temperature range Storage temperature range PARAMETER RATING 0.5 to +7.0 0.5 to +7.0 30 to +5 0.5 to VCC 16 0 to +70 65 to +150 UNIT V V mA V mA °C °C
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC VIH VIL IIK IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free-air temperature range 0 PARAMETER MIN 4.5 2.0 0.8 18 0.4 8 +70 NOM 5.0 MAX 5.5 UNIT V V V mA mA mA °C
1991 Feb 08
3
Philips Semiconductors
Product specification
Quad D flip-flop
74ALS175
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL VOH VOL VIK II IIH IIL IO ICC PARAMETER High-level output voltage Low-level output voltage output voltage Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current Output current3 Supply current (total) TEST CONDITIONS1 CONDITIONS VCC±10%, VIL = MAX, VIH = MIN, IOH = MAX VCC = MIN, VIL = MAX, , , VIH = MIN VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V VCC = MAX, VO = 2.25V VCC = MAX 30 7 IOL = 4mA IOL = 8mA LIMITS MIN VCC 2 0.25 0.35 0.73 0.4 0.50 1.5 100 20 0.1 112 14 TYP2 MAX UNIT V V V V µA µA mA mA mA
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
AC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500 MIN fMAX tPLH tPHL tPLH tPHL Maximum clock frequency Propagation delay CP to Qn or CP to Qn Propagation delay, MR to Qn Propagation delay, MR to Qn Waveform 1 Waveform 1 Waveform 2 Waveform 2 60 3.0 5.0 3.0 8.0 13.0 16.0 13.0 18.0 MAX MHz ns ns ns UNIT
AC SETUP REQUIREMENTS
LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500 MIN tsu(H) tsu(L) th(H) th(L) tw(H) tw(L) tw(L) tREC Setup time, High or Low Dn to CP Hold time, High or Low Dn to CP CP pulse width, High or Low MR pulse width, Low Recovery time, MR to CP Waveform 3 Waveform 3 Waveform 1 Waveform 2 Waveform 2 6.0 6.0 0.0 0.0 8.0 8.0 6.0 6.0 MAX ns ns ns ns ns UNIT
1991 Feb 08
4
Philips Semiconductors
Product specification
Quad D flip-flop
74ALS175
AC WAVEFORMS
For all waveforms, VM = 1.3V. The shaded areas indicate when the input is permitted to change for predictable output performance.
1/fmax MR CP VM tw(H) tPHL VM tPLH Qn VM tw(L) tPLH CP VM tPHL tPHL Qn tPLH VM VM VM tw(L) tREC VM VM VM
Qn
VM
SF00722
Qn
VM
Waveform 1. Propagation Delay for Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency
SF00723
Waveform 2. Master Reset Pulse Width, Master Reset to Output Delay, and Master Reset to Clock Recovery Time
Dn
VM tsu(H)
VM th(H)
VM tsu(L)
VM th(L)
CP
VM
VM
SC00064
Waveform 3. Data Setup and Hold Times
TEST CIRCUIT AND WAVEFORMS
V CC NEGATIVE PULSE V IN PULSE GENERATOR RT D.U.T. VOUT 90% VM 10% tTHL (tff) CL RL tw VM 10% tTLH (tr ) 0.3V 90% AMP (V)
tTLH (tr ) 90%
tTHL (tf ) AMP (V) 90% VM tw 10% 0.3V
Test Circuit for Totem-pole Outputs
POSITIVE PULSE 10%
VM
DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
Input Pulse Definition INPUT PULSE REQUIREMENTS Family Amplitude VM 74ALS 3.5V 1.3V Rep.Rate 1MHz tw 500ns tTLH 2.0ns tT H L 2.0ns
SC00005
1991 Feb 08
5
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