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Part: 74F8960X
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Philips Semiconductors FAST Products
Product specification
Octal latched bidirectional Futurebus transceivers (3-State + open-collector)
74F8960/74F8961
FEATURES
· Octal latched transceiver · Drives heavily loaded backplanes with
equivalent load impedances down to 10
DESCRIPTION
The 74F8960 and 74F8961 are octal bidirectional latched transceivers and are intended to provide the electrical interface to a high performance wiredOR bus. The B port inverting drivers are lowcapacitance open collector with controlled ramp and are designed to sink 100mA from 2 volts. The B port inverting receivers have a 100 mV threshold region and a 4ns glitch filter. The B port interfaces to `Backplane Transceiver Logic' (BTL). BTL features a reduced (1V to 2V) voltage swing for lower power consumption and a series diode on the drivers to reduce capacitive loading. Incident switching is employed, therefore BTL propagation delays are short. Although the
voltage swing is much less for BTL, so is its receiver threshold region, therefore noise margins are excellent. BTL offers low power consumption, low ground bounce, EMI and crosstalk, low capacitive loading, superior noise margin and low propagation delays. This results in a high bandwidth, reliable backplane. The 74F8960 and 74F8961 A ports have TTL 3state drivers and TTL receivers with a latch function. A separate Highlevel control input (VX) is provided to limit the A side output level to a given voltage level (such as 3.3V). For 5.0V systems, VX is simply tied to VCC. The 74F8961 is the noninverting version of 74F8960.
· High drive (100mA) open collector drivers
on B port
· Reduced voltage swing (1 volt) produces
less noise and reduces power consumption
· High speed operation enhances
performance of backplane buses and facilitates incident wave switching
· Compatible with IEEE futurebus standards · Built-in precision band-gap reference
provides accurate receiver thresholds and improved noise immunity
· Controlled output ramp and multiple GND
pins minimize ground bounce
· Glitch-free power up/down operation
TYPE 74F8960 74F8961 TYPICAL PROPAGATION DELAY 6.5ns 6.5ns TYPICAL SUPPLY CURRENT( TOTAL) 80mA 80mA
ORDERING INFORMATION
DESCRIPTION 28pin plastic DIP (300 mil)1 28pin PLCC1 NOTE: Thermal mounting techiques are recommended. ORDER CODE COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F8960N, N748961N N74F8960A, N74F8961A
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS A0 A8 B0 B8 OEA OEB0, OEB1 LE A0 A7 PNP latched inputs Data inputs with threshold circuitry A output enable input (active high) B output enable inputs (active low) Latch enable input (active low) 3state outputs DESCRIPTION 74F (U.L.) HIGH/LOW 3.5/0.117 5.0/0.167 1.0/0.033 1.0/0.033 1.0/0.033 150/40 OC/166.7 LOAD VALUE HIGH/LOW 70µA/70µA 100µA/100µA 20µA/20µA 20µA/20µA 20µA/20µA 3mA/24mA OC/100mA
B0 B7 Open collector outputs NOTES: 1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state. 2. OC = Open collector.
December 19, 1990
1
853-1120 01322
Philips Semiconductors FAST Products
Product specification
Octal latched bidirectional Futurebus transceivers (3-State + open-collector)
PIN CONFIGURATION
74F8960
V CC 1 OEA 2 A0 3 GND 4 A1 5 A2 6 A3 7 GND 8 A4 9 A5 10 GND 11 A6 12 A7 13 VX 14 28 LE 27 B0 26 B1 25 GND 24 B2 23 B3 22 GND 21 B4 20 B5 19 B6 18 GND 17 B7 16 OEB1 15 OEB0 A1 A2 5 6 7 8 9 PLCC GND A0 OEA VCC LE 4 3 2 1 28 B0 B1 27 26 25 GND 24 B2 23 B3 22 GND 21 B4 20 B5 19 B6 12 A6 13 14 15 16 17 18 27 15 2 28 16
74F8960/74F8961
PIN CONFIGURATION PLCC
74F8960
LOGIC SYMBOL
74F8960
3 5 6 7 9 10 12 13
A0 A1 A2 OEB0 OEA LE OEB1
A3 A4 A5
A6 A7
A3
GND A4
A5 10 GND 11
B0 B1 B2 B3 B4 B5
B6 B7
A7 VX OEB2 OEB1 B7 GND
26 24
23
21 20
19 17
VCC = Pin 1, VX = Pin 14 GND = Pin 4, 8, 11, 18, 22, 25
PIN CONFIGURATION
74F8961
V CC 1 OEA 2 A0 3 GND 4 A1 5 A2 6 A3 7 GND 8 A4 9 A5 10 GND 11 A6 12 A7 13 VX 14 28 LE
PIN CONFIGURATION PLCC
74F8961
LOGIC SYMBOL
74F8961
3 5 6 7 9 10 12 13
27 B0 26 B1 25 GND 24 B2 23 B3 22 GND 21 B4 20 B5 19 B6 18 GND 17 B7 16 OEB1 15 OEB0 A1 A2 5 6
GND A0 OEA VCC LE 4 3 2 1 28
B0 B1 27 26 25 GND 24 B2 23 B3 15 2 28 16 A0 A1 A2 A3 A4 A5 OEB0 OEA LE OEB1 B0 B1 B2 B3 B4 B5 B6 B7 A6 A7
A3 7
GND A4 8 9 PLCC
22 GND 21 B4 20 B5 19 B6
A5 10 GND 11 12 A6 13 14 15 16 17 18
27
26 24
23
21 20
19 17
A7 VX OEB2 OEB1 B7 GND
VCC = Pin 1, VX = Pin 14 GND = Pin 4, 8, 11, 18, 22, 25
December 19, 1990
2
Philips Semiconductors FAST Products
Product specification
Octal latched bidirectional Futurebus transceivers (3-State + open-collector)
IEC/IEEE SYMBOL FOR 74F8960
74F8960
15 16 28 2 C1 EN3 27 & EN2 15 16 28 2 C1 EN3 &
74F8960/74F8961
IEC/IEEE SYMBOL FOR 74F8961
74F8961
EN2
3
1D 3
2
3
1D 3
2
27
5 6 7 9 10 11 13
26 24 23 21 20 19 17
5 6 7 9 10 11 13
26 24 23 21 20 19 17
PIN DESCRIPTION
SYMBOL A0 A7 B0 B7 OEB0 OEB1 LE VX PINS 3, 5, 6, 7, 9, 10, 12, 13 27, 26, 24, 23, 21, 20, 19, 17 15 16 28 14 TYPE I/O I/O Input Input Input Input NAME AND FUNCTION PNP latched input/3state output (with VX control option) Data input with special threshold circuitry to reject noise/ open collector output, high current drive Enables the B outputs when both pins are low Enables the A outputs when high Latched when high (a special feature is buillt in for proper enabling times) Clamping voltage keeping VOH from rising above VX (VX = Vcc for normal use)
December 19, 1990
3
Philips Semiconductors FAST Products
Product specification
Octal latched bidirectional Futurebus transceivers (3-State + open-collector)
LOGIC DIAGRAM
74F9860 OEB0 15 OEB0 15 74F9861
74F8960/74F8961
OEB1
16
OEB1
16
OEA 2
OEA 2
LE 28 3
LE 28 3
A0
Data LE
Q
27 B0
A0
Data LE
Q
27 B0
A1
5
Data LE
Q
26 B1
A1
5
Data LE
Q
26 B1
A2
6
Data LE
Q
24 B2
A2
6
Data LE
Q
24 B2
A3
7
Data LE
Q
23 B3
A3
7
Data LE
Q
23 B3
A4
9
Data LE
Q
21 B4
A4
9
Data LE
Q
21 B4
A5 10
Data LE
Q
20 B5
A5 10
Data LE
Q
20 B5
A6 12
Data LE
Q
19 B6
A6 12
Data LE
Q
19 B6
A7 13
Data LE
Q
17 B7
A7 13
Data LE
Q
17 B7
VCC = Pin 1, VX = Pin 14, GND = Pin 4, 8, 11, 18, 22, 25
December 19, 1990
4
Philips Semiconductors FAST Products
Product specification
Octal latched bidirectional Futurebus transceivers (3-State + open-collector)
FUNCTION TABLE FOR 74F8960
INPUTS An H L X H l X H l X NOTES: 1. H = 2. L = 3. X = 4. = 5. Z = 6. Qn = 7. (1) = 8. (2) = 9. H**= 10. B* = Bn* X X X H L X X X H L H L X X X H L H L LE L L H L H H H L L H L L H H L L H L L H H OEA L L L H H H H L L L H H H H L L L H H H H OEB 0 L L L L L L L H H H H H H H X X X X X X X OEB 1 L L L L L L L X X X X H H H H H H H H H H LATCH STATE H L Qn (1) H (2) H (2) Qn H l Qn H L Qn Qn H l Qn H L Qn Qn OUTPUTS An Z Z Z (1) H L Qn Z Z Z H L H L Z Z Z H L H L Bn L H** Qn (1) Z(2) Z(2) Qn Z Z Z Z Z Z Z Z Z Z Z Z Z Z B 3state, data from B to A B and A 3state B 3state, data from B to A B and A 3state Latch state to A and B A 3state, latched data to B Feedback: A to B, B to A A 3state, data from A to B
74F8960/74F8961
OPERATING MODE
Preconditioned latch enabling data transfer from B to A
Highvoltage level Lowvoltage level Don't care Input not externally driven High impedance (off) state High or low voltage level one setup time prior to the lowtohigh LE transition. Condition will cause a feedback loop path: A to B and B to A. The latch must be preconmditioned such that B inputs may assume a high or low level while OEB0 and OEB1 are low and LE is high. Goes to level of pullup voltage. Precaution should be taken to insure the B inputs do not float. If they do they are equal to low state.
December 19, 1990
5
Others parts begin by 74
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