|
Details, datasheet, quote on part number:74HC237N
| |
Datasheet text preview:
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
· The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications · The IC06 74HC/HCT/HCU/HCMOS Logic Package Information · The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT237 3-to-8 line decoder/demultiplexer with address latches
Product specification File under Integrated Circuits, IC06 December 1990
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer with address latches
FEATURES · Combines 3-to-8 decoder with 3-bit latch · Multiple input enable for easy expansion or independent controls · Active HIGH mutually exclusive outputs · Output capability: standard · ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT237 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
74HC/HCT237
The 74HC/HCT237 are 3-to-8 line decoder/demultiplexers with latches at the three address inputs (An). The "237" essentially combines the 3-to-8 decoder function with a 3-bit storage latch. When the latch is enabled (LE = LOW), the "237" acts as a 3-to-8 active LOW decoder. When the latch enable (LE) goes from LOW-to-HIGH, the last data present at the inputs before this transition, is stored in the latches. Further address changes are ignored as long as LE remains HIGH. The output enable input (E1 and E2) controls the state of the outputs independent of the address inputs or latch operation. All outputs are HIGH unless E1 is LOW and E2 is HIGH. The "237" is ideally suited for implementing non-overlapping decoders in 3-state systems and strobed (stored address) applications in bus oriented systems.
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL tPHL / tPLH PARAMETER propagation delay An to Yn LE to Yn E1 to Yn E2 to Yn CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 16 19 14 14 3.5 60 19 21 17 17 3.5 63 ns ns ns ns pF pF HCT UNIT
December 1990
2
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer with address latches
PIN DESCRIPTION PIN NO. 1, 2, 3 4 5 6 8 15, 14, 13, 12, 11, 10, 9, 7 16 SYMBOL A0 to A2 LE E1 E2 GND Y0 to Y7 VCC NAME AND FUNCTION data inputs latch enable input (active LOW) data enable input (active LOW) data enable input (active HIGH) ground (0 V) multiplexer outputs positive supply voltage
74HC/HCT237
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer with address latches
74HC/HCT237
Fig.4 Functional diagram.
FUNCTION TABLE INPUTS LE H X X L L L L L L L L Notes 1. H = HIGH voltage level L = LOW voltage level X = don't care E1 L H X L L L L L L L L E2 H X L H H H H H H H H A0 X X X L H L H L H L H A1 X X X L L H H L L H H A2 X X X L L L L H H H H L L H L L L L L L L L L L H L L L L L L L L L L H L L L L L Y0 Y1 Y2 OUTPUTS Y3 stable L L L L L H L L L L L L L L L L H L L L L L L L L L L H L L L L L L L L L L H L L L L L L L L L L H Y4 Y5 Y6 Y7
December 1990
4
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer with address latches
74HC/HCT237
Fig.5 Logic diagram.
December 1990
5
|
|
