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Part: 74LCX74T
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Datasheet: Download 74LCX74T datasheet File size : 201 kB
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74LCX74
LOW VOLTAGE CMOS DUAL D-TYPE FLIP FLOP WITH 5V TOLERANT INPUTS
PRELIMINARY DATA
s s
s
s
s s
s
s
s s
5V TOLERANT INPUTS HIGH SPEED: fMAX = 150 MHz (MAX.) at VCC = 3V POWER-DOWN PROTECTION ON INPUTS AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24 mA (MIN) PCI BUS LEVELS GUARANTEED AT 24mA BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2.0V to 3.6V (1.5V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 74 LATCH-UP PERFORMANCE EXCEEDS 500mA ESD PERFORMANCE: HBM >2000V; MM > 200V
M (Micro Package)
T (TSSOP Package)
ORDER CODES : 74LCX74M 74LCX74T 5V signal enviroment for inputs. A signal on the D INPUT is transferred to the Q OUTPUT during the p ositive going transition of the clock pulse. CLEARE and PRESET are indepen dent of the clock and accomplished by a low setting on the appropriate input. It has same speed performance at 3.3V than 5V, AC/ACT family, combined with a lower power consumption. All inputs and outputs are equipped with protection circuits against s tatic discharge, giving them 2KV ESD immunity and transient excess voltage.
DESCRIPTION The LCX74 is a low voltage CMOS OCTAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and high speed 3.3V applications; it can be interfaced to
PIN CONNECTION AND IEC LOGIC SYMBOLS
January 1997
1/11
74LCX74
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PI N N o 1, 13 2, 12 3, 11 S Y M BO L 1CLR, 2CLR 1D, 2D 1CK, 2CK NAM E AN D F UNC T I O N As ync ro nous Res et Direct In put Data In puts Clock I nput (LO W-t o -HIG H , EdgeTr iggered) As ync ro nous Se t - D ir ect In put Tr ue F lip-Flo p Ou tpu s Complement Fli p- Flo p Ou tput s Gr ound (0 V) Po siti ve Su pply Vo lt age
TRUTH TABLE
I N P UT S CL R L H L H H H PR H L L H H H D X X X L H X CK X X X O U T PU T S Q L H H L H Qn Q H L H H L Qn NO CHANGE CLEAR PR ESET F UN CT I O N
4, 10 5, 9 6, 8 7 14
1PR, 2PR 1Q, 2Q 1Q, 2Q GND VCC
X: Don't Care
LOGIC DIAGRAMS
This logic diagram has not be used to esimate propagation delays
2/11
74LCX74
ABSOLUTE MAXIMUM RATINGS
S y mb o l VCC VI VO VO II K IOK IO ICC IGND Tstg TL Supply Vo lt age DC In put Volta ge DC Ou tpu t Vo lt age ( VCC= 0V) DC Ou tpu t Vo lt age ( High or L ow S tat e) (not e1) DC In put Diode Curr ent DC Ou tpu t D iode C u rrent (n ot e2) DC Ou tpu t So u rce/ Si nk Current DC Su pply Curr ent per S upply P in DC Gr ound Current per S upply Pin Stor age T emperat ur e Lead T empe ratu re (10 se c) P arame t er V al u e -0.5 to + 7.0 -0.5 to + 7.0 -0.5 to + 7.0 -0.5 t o VCC + 0.5 - 50 ± 50 ± 50 ± 100 ± 100 -65 to +150 300 Un i t V V V V mA mA mA mA mA
o o
C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. 1) IO absolute maximum rating must be observed 2) VO VCC
RECOMMENDED OPERATING CONDITIONS
Sy m b o l VCC VI VO VO IOH, IOL IOH, IOL Top dt/dv In put V oltage Ou tp ut Vo lt age (VCC = 0V) Ou tp ut Vo lt age (High o r L ow S t at e) High or L ow Level O utput C ur rent (V CC = 3. 0 t o 3.6V ) High or L ow Level O utput C ur rent (V CC = 2. 7 t o 3.0V ) Op er ating T emperat ur e: In put T ra nsit ion R ise o r Fall R a te ( VCC = 3.0 V) ( note 2) P ara met er Su pply Volt age (note 1 ) V al u e 2.0 to 3.6 0 to 5.5 0 to 5.5 0 to VCC ± 24 ± 12 -40 to +85 0 to 10 Un i t V V V V mA mA
o
C
ns/V
1) Truth Table guaranteed: 1.5V to 3.6V 2) VIN from 0.8V to 2.0V
3/11
74LCX74
DC SPECIFICATIONS
S ym b o l P a ra m e t er V CC (V ) VIH VIL VOH High Level I nput V o ltage Low L evel Input Volta ge High Level O ut put Volta ge 2. 7 t o 3. 6 2.7 to 3.6 2.7 3.0 VOL Low L evel Outp ut Volt age 2.7 to 3.6 2.7 3.0 3.0 II Ioff ICC Input Leakage C urrent Power O f f Leak age C u rrent Quies cent Supply C u rrent 2. 7 t o 3. 6 0 2.7 to 3.6 VI = V I H or VIL T est C o n d i t i o n s V al u e - 40 t o 85 C Mi n. 2.0 0.8 IO=-100 µA V CC - 0. 2 IO=-12 mA IO=-18 mA IO=-24 mA VI = V I H or VIL IO=100 µA IO=12 mA IO=16 mA IO=24 mA VI = 0 to 5.5 V VI or VO = 5.5V VI = VCC or GND VI or VO = 3.6 to 5.5V ICC ICC inc r. per input 2.7 to 3.6 VIH = VCC -0.6V 2.2 2.4 2.2 0.2 0.4 0.4 0.55 ±5 100 10 ±10 500 µA µA µA µA V V M ax. V V
o
Unit
DYNAMIC SWITCHING CHARACTERISTICS
S ym b o l P arame t er V CC (V) VOLP VOLV Dynam ic Low V oltag e Quiet O utput (not e 1 ) 3.3 C L = 50 pF V IL = 0 V V I H = 3 . 3V T est Co n d i t i o n s M in. V al u e T A = 25 C T yp . 0.8 -0.8 V M a x.
o
Unit
1) Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is measured in the LOW state.
4/11
74LCX74
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 , Input tr = t f = 2.5 ns)
S ym b o l P ar am e t er V CC ( V) tPLH tPHL tPLH tPHL ts th tw trec fMAX tOSLZ tOSHL Propagati on D e lay T ime CK to Q or Q Propagati on D e lay T ime PR or C L R t o Q or Q Setu p T ime, HI Gh or LO W level D n to CP Hold Ti me, HI Gh o r LOW level D n to CP CP Pu lse W idt h, H I GH or L OW , PR or C L R Pulse W idt h, LO W Recov ery T im e PR or CLR to C K Clock P u lse F re quency Out put to Ou tp ut Sk ew T im e (not e 1 , 2) 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 T est Co n d i t i o n W av ef o rm V al u e - 40 t o 85 C M i n . M ax. 1.5 8.0 1.5 1.5 1.5 2.5 2.5 1.5 1.5 3.3 3.3 0 0 150 1.0 7.0 8.0 7.0
o
Unit
1 1 1 1 3 1, 3 1
ns ns ns ns ns ns M Hz ns
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tpHLn|) 2) Parameter guaranteed by design
CAPACITIVE CHARACTERISTICS
S ym b o l P arame t er V CC (V ) CIN C PD Input Capacita nce Power D is sipat ion Capac ita nce (note 1) 3.3 3.3 VIN = 0 to VCC fIN = 10MHz VIN = 0 or VCC T est C o n d i t i o n s Min . Va l u e TA = 25 oC Typ. 6 40 M ax. pF pF Unit
1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. Average operting current can be obtained by the following equation. ICC(opr) = CPD · VCC · fIN + ICC/n (per circuit)
5/11
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