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Part: 74LV4040PW
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INTEGRATED CIRCUITS
74LV4040 12-stage binary ripple counter
Product specification IC24 Data Handbook 1998 Jun 23
Philips Semiconductors
Philips Semiconductors
Product specification
12-stage binary ripple counter
74LV4040
FEATURES
· Optimized for Low Voltage applications: 1.0 to 5.5V · Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V · Typical VOLP (output ground bounce) t 0.8V @ VCC = 3.3V, · Typical VOHV (output VOH undershoot) u 2V @ VCC = 3.3V, · Frequency dividing circuits · Time delay circuits · Control counters · Output capability: standard · ICC category: MSI
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr =tf v2.5 ns SYMBOL PARAMETER Propagation delay CP to Q0 Qn to Qn+1 MR to Qn Maximum clock frequency Input capacitance Power dissipation capacitance per gate Tamb = 25°C Tamb = 25°C
DESCRIPTION
The 74LV4040 is a lowvoltage Sigate CMOS device and is pin and function compatible with 74HC/HCT4040. The 74LV4040 is a 12-stage binary ripple counter with a click input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered parallel outputs (Q0 to Q11). The counter is advanced on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop.
CONDITIONS CL = 15pF VCC = 3.3V
TYPICAL 12 7 16 100 3.5
UNIT
tPHL/tPLH fmax CI CP D
ns
MHz pF pF
Notes 1 and 2
30
NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) VCC2 x fi )S (CL VCC2 fo) where: PD = CPD fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; VCC2 fo) = sum of the outputs. S (CL 2. The condition is VI = GND to VCC
ORDERING INFORMATION
PACKAGES 16-Pin Plastic DIL 16-Pin Plastic SO 16-Pin Plastic SSOP Type II 16-Pin Plastic TSSOP Type I TEMPERATURE RANGE 40°C to +125°C 40°C to +125°C 40°C to +125°C 40°C to +125°C OUTSIDE NORTH AMERICA 74LV4040 N 74LV4040 D 74LV4040 DB 74LV4040 PW NORTH AMERICA 74LV4040 N 74LV4040 D 74LV4040 DB 74LV4040PW DH PKG. DWG. # SOT38-4 SOT109-1 SOT338-1 SOT403-1
1998 Jun 23
2
853-2075 19619
Philips Semiconductors
Product specification
12-stage binary ripple counter
74LV4040
PIN CONFIGURATION
LOGIC SYMBOL
Q0 9 7 6 5 3 2 4 13 12 14 15 1
Q11 Q5 Q4 Q6 Q3 Q2 Q1 GND
1 2 3 4 5 6 7 8
16 VCC 15 Q10 14 Q9 13 Q7 12 Q8 11 MR 10 CP 9 Q0 11 MR 10 CP
Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11
SV00316
SV00317
Figure 1. Pin configuration
Figure 3. Logic symbol
PIN DESCRIPTION
PIN NUMBER 9, 7, 6, 5, 3, 2, 4, 13, 12, 14, 15, 1 8 10 11 16 SYMBOL FUNCTION
FUNCTIONAL DIAGRAM
Q0 to Q11 GND CP MR VCC
Parallel outputs Ground (0V) Clock input (HIGH-to-LOW, edgetriggered) Master reset input (active HIGH) Positive supply voltage
10 11
CP
T 12-STAGE COUNTER
MR
CD Q0 Q1 9 7 Q2 Q3 5 5 Q4 3 Q5 2 Q6 4 Q7 13 Q8 12 Q9 14 Q10 Q11 15 1
LOGIC SYMBOL (IEEE/IEC)
SV00319
CTR12 10 11 + CT=0 0 9 7 5 5 3 2 CT 4 13 12 14 15 11 1 MR CP FF0 Q T Q RD T Q RD FF3 Q FF11 Q T Q RD
Figure 4. Functional diagram
LOGIC DIAGRAM
SV00318
Figure 2. IEC Logic symbol
Q0 Q1 Q11
SV00320
Figure 5. Logic diagram
1998 Jun 23
3
Philips Semiconductors
Product specification
12-stage binary ripple counter
74LV4040
1 CP INPUT
2
4
8
16
32
64
128
256
512
1.024
2.048
4.096
MR INPUT
Q0 OUTPUT
Q1 OUTPUT
Q2 OUTPUT
Q3 OUTPUT
Q4 OUTPUT
Q5 OUTPUT
Q6 OUTPUT
Q7 OUTPUT
Q8 OUTPUT
Q9 OUTPUT
Q10 OUTPUT
Q11 OUTPUT
SV00310
Figure 6. Timing diagram
FUNCTION TABLE
INPUTS CP ° ± X MR L L H OUTPUTS Q0, Q3 to Q13 no change count L
NOTES: H = HIGH voltage level L = LOW voltage level X = Don't care ° = LOW -to-HIGH clock transition ± = HIGH-to-LOW clock transition
1998 Jun 23
4
Philips Semiconductors
Product specification
12-stage binary ripple counter
74LV4040
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL VCC ±IIK ±IOK ±IO ±IGND, ±ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC output diode current DC output source or sink current standard outputs DC VCC or GND current for types with standard outputs Storage temperature range Power dissipation per package plastic DIL plastic mini-pack (SO) plastic shrink mini-pack (SSOP and TSSOP) for temperature range: 40 to +125°C above +70°C derate linearly with 12mW/K above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K VI VCC + 0.5V VO VCC + 0.5V 0.5V < VO < VCC + 0.5V CONDITIONS RATING 0.5 to +7.0 20 50 25 50 65 to +150 750 500 400 UNIT V mA mA mA mA °C mW
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VI VO Tamb Input voltage Output voltage Operating ambient temperature range in free air Input rise and fall times See DC and AC characteristics VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V to 5.5V PARAMETER DC supply voltage CONDITIONS See Note1 MIN 1.0 0 0 40 40 TYP. 3.3 MAX 5.5 VCC VCC +85 +125 500 200 100 50 UNIT V V V °C
tr, tf
ns/V
NOTE: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
1998 Jun 23
5
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