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Part: 74LVCH2373APW
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Datasheet: Download 74LVCH2373APW datasheet File size : 143 kB
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INTEGRATED CIRCUITS
74LVC2373A 74LVCH2373A Octal D-type transparent latch with 5-volt tolerant inputs/outputs; damping resistor (3-State)
Product specification IC24 Data Handbook 1997 Mar 12
Philips Semiconductors
Philips Semiconductors
Product specification
Octal D-type transparent latch with 5-volt tolerant inputs/outputs; damping resistor (3-State)
74LVC2373A 74LVCH2373A
FEATURES
· 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic · Supply voltage range of 2.7V to 3.6V · Complies with JEDEC standard no. 8-1A · CMOS low power consumption · Direct interface with TTL levels · High impedance when VCC = 0V · Bushold on all data inputs (74LVCH2373A only) · Integrated 30W damping resistor
DESCRIPTION
The 74LVC2373A/74LVCH2373A is a high performance, low-power, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in a mixed 3.3V/5V environment. The 74LVC2373A/74LVCH2373A is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all internal latches. The `2373' consists of eight D-type transparent latches with 3-State true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches.
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr = tf v2.5 ns SYMBOL tPHL/tPLH CI CP D PARAMETER Propagation delay Dn to Qn LE to Qn Input capacitance Power dissipation capacitance per latch Notes 1, 2 CONDITIONS CL = 50pF VCC = 3.3V TYPICAL 4.4 5.0 5.0 20 UNIT ns pF pF
NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi ) (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL × VCC2 × fo) = sum of the outputs. 2. The condition is VI = GND to VCC.
ORDERING AND PACKAGE INFORMATION
PACKAGES 20-Pin Plastic SO 20-Pin Plastic SSOP Type II 20-Pin Plastic TSSOP Type I 20-Pin Plastic SO 20-Pin Plastic SSOP Type II 20-Pin Plastic TSSOP Type I TEMPERATURE RANGE 40°C to +85°C 40°C to +85°C 40°C to +85°C 40°C to +85°C 40°C to +85°C 40°C to +85°C OUTSIDE NORTH AMERICA 74LVC2373A D 74LVC2373A DB 74LVC2373A PW 74LVCH2373A D 74LVCH2373A DB 74LVCH2373A PW NORTH AMERICA 74LVC2373A D 74LVC2373A DB LVC2373APW DH 74LVCH2373A D 7LVCH2373A DB VCH2373APW DH PKG. DWG. # SOT163-1 SOT339-1 SOT360-1 SOT163-1 SOT339-1 SOT360-1
1997 Mar 12
2
8531940 17843
Philips Semiconductors
Product specification
Octal D-type transparent latch with 5-volt tolerant inputs/outputs; damping resistor (3-State)
74LVC2373A 74LVCH2373A
PIN CONFIGURATION
OE Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q7
LOGIC SYMBOL
11 LE 3 D7 D6 Q6 Q5 D5 D4 Q4 LE 4 7 8 13 14 17 18 D0 D1 D2 D3 D4 D5 D6 D7 OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19
SV00657
1
SV00658
PIN DESCRIPTION
PIN NUMBER 1 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 10 11 20 SYMBOL OE Q0Q7 D0D7 GND LE VCC FUNCTION Output enable input (active LOW) 3-State latch outputs
FUNCTIONAL DIAGRAM
3 4 7 D0 D1 D2 D3 D4 D5 D6 D7 LATCH 1 to 8 3STATE OUTPUTS Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19
Data inputs Ground (0V) Latch enable input (active HIGH) Positive supply voltage
8 13 14 17 18
LOGIC SYMBOL (IEEE/IEC)
11 1 C1 EN1
11 1
LE OE
SV00660
3 1D 2
4 7 8 13 14 17 18
5 6 9 12 15 16 19
FUNCTION TABLE
OPERATING MODES Enable and read register (transparent mode) Latch and read register Latch register and disable outputs INPUTS OE L L L L H H LE H H L L L L Dn L H I h I h INTERNAL LATCHES L H L H L H OUTPUTS Q0 to Q7 L H L H Z Z
SV00659
H = HIGH voltage level h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition L = LOW voltage level I = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition X = Don't care Z = High impedance OFF-state
1997 Mar 12
3
Philips Semiconductors
Product specification
Octal D-type transparent latch with 5-volt tolerant inputs/outputs; damping resistor (3-State)
74LVC2373A 74LVCH2373A
LOGIC DIAGRAM
D0 D1 D2 D3 D4 D5 D6 D7
Q D LATCH 1 LE LE LE OE
Q D LATCH 2 LE LE
Q D LATCH 3 LE LE
Q D LATCH 4 LE LE
Q D LATCH 5 LE LE
Q D LATCH 6 LE LE
Q D LATCH 7 LE LE
Q D LATCH 8 LE LE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
SV00661
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VCC VI VI/O VO Tamb tr, tf PARAMETER DC supply voltage (for max. speed performance) DC supply voltage (for low-voltage applications) DC input voltage range DC input voltage range for I/Os DC output voltage range Operating free-air temperature range Input rise and fall times VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V CONDITIONS LIMITS MIN 2.7 1.2 0 0 0 40 0 0 MAX 3.6 3.6 5.5 VCC VCC +85 20 10 UNIT V V V V V °C ns/V
ABSOLUTE MAXIMUM RATINGS1
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V). SYMBOL VCC IIK VI VI/O IOK VOUT VOUT IOUT IGND, ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC input voltage DC input voltage range for I/Os DC output diode current DC output voltage; output HIGH or LOW DC output voltage; output 3-State DC output source or sink current DC VCC or GND current Storage temperature range Power dissipation per package plastic mini-pack (SO) plastic shrink mini-pack (SSOP and TSSOP) above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K VO uVCC or VO t 0 Note 2 Note 2 VO = 0 to VCC VI t0 Note 2 CONDITIONS RATING 0.5 to +6.5 50 0.5 to +5.5 0.5 to VCC +0.5 ±50 0.5 to VCC +0.5 0.5 to +6.5 ±50 ±100 60 to +150 500 500 UNIT V mA V V mA V V mA mA °C
mW
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1997 Mar 12
4
Philips Semiconductors
Product specification
Octal D-type transparent latch with 5-volt tolerant inputs/outputs; damping resistor (3-State)
74LVC2373A 74LVCH2373A
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0V). LIMITS SYMBOL PARAMETER VCC = 1.2V VCC = 2.7 to 3.6V VCC = 1.2V VCC = 2.7 to 3.6V VCC = 3.0V; VI = VIH or VIL; IO = 100µA VOH HIGH level output voltage VCC = 3.0V; VI = VIH or VIL; IO = 12mA VCC = 3.0V; VI = VIH or VIL; IO = 24mA VCC = 2.7V; VI = VIH or VIL; IO = 6mA7 VOH HIGH level output voltage VCC = 3.0V; VI = VIH or VIL; IO = 100µA7 VCC = 3.0V; VI = VIH or VIL; IO = 12mA7 VOL LOW level output voltage level output voltage VCC = 3.0V; VI = VIH or VIL; IO = 100µA VCC = 3.0V; VI = VIH or VIL; IO = 24mA VCC = 2.7V; VI = VIH or VIL; IO = 6mA7 VOL II IIHZ/IILZ IOZ ICC ICC IBHL IBHH IBHLO IBHHO LOW level output voltage Input leakage current Input current for common I/O pins 3-State output OFF-state current Quiescent supply current Additional quiescent supply current per input pin Bushold LOW sustaining current2, 3, 4 Bushold HIGH sustaining current2, 3, 4 Bushold LOW overdrive current2, 3, 5 Bushold HIGH overdrive current2, 3, 5 VCC = 3.0V; VI = VIH or VIL; IO = 100µA7 VCC = 3.0V; VI = VIH or VIL; IO = VCC = 3.6V; VI = 5.5V or GND VCC = 3.6V; VI = VCC or GND VCC = 3.6V; VI = VIH or VIL; VO = VCC or GND VCC = 3.6V; VI = VCC or GND; IO = 0 VCC = 2.7V to 3.6V; VI = VCC 0.6V; IO = 0 VCC = 3.0V; VI =0.8V VCC = 3.0V; VI =2.0V VCC = 3.6V VCC = 3.6V 75 75 500 500 12mA7 Not for I/O pins ±0.1 ±0.1 0.1 0.1 5 GND VCC*0.2 VCC*0.6 VCC*1.0 VCC*0.5 VCC*0.2 VCC*0.8 GND 0.20 0.55 0.40 0.20 0.55 ±5 ±15 ±10 20 500 µA µA µA µA µA µA µA µA µA V V VCC V VCC V TEST CONDITIONS Temp = -40°C to +85°C MIN VIH VIL HIGH level Input voltage level Input voltage LOW level Input voltage level Input voltage VCC 2.0 GND 0.8 TYP1 MAX V V UNIT
NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. 2. Valid for data inputs of bushold parts (LVCH-A) only. 3. For data inputs only, control inputs do not have a bushold circuit. 4. The specified sustaining current at the data inputs do not have a bushold circuit. 5. The specified overdrive current at the data input forces the data input to the opposite logic input state. 6. For bushold parts, the bushold circuit is switched off when VI exceeds VCC allowing 5.5V on the input terminal. 7. For data outputs of damping resistor parts only.
1997 Mar 12
5
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