|
|
Part: 74LVQ245T
Category:
Description:
Company:
Datasheet: Download 74LVQ245T datasheet File size : 143 kB
Request For quote: Find where to buy 74LVQ245T
Datasheet text preview:
74LVQ245
LOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER (3-STATE)
s s s
s s
s
s s
s
s
s
HIGH SPEED: tPD = 6 ns (TYP.) at VCC = 3.3V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 5 µA (MAX.) at TA = 25 oC LOW NOISE: VOLP = 0.5V (TYP.) at VCC = 3.3V 75 TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 12 mA (MIN) PCI BUS LEVELS GUARANTEED AT 24mA BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 245 IMPROVED LATCH-UP IMMUNITY
M (Micro Package)
T (TSSOP Package)
ORDER CODES : 74LVQ24 5M 74LVQ245 T This IC is intende d for two-way asynchronous communication beetwen data buses; the direction of data trasmission is determined by DIR input. The enable input G can be used to disable the device so that the buses are effectively isolated. All inputs and outputs are equipped with protection circuits against s tatic discharge, giving them 2KV ESD immunity and transient excess voltage. IT IS PROHIBITED TO APPLY A SIGNAL TO A TERMINAL WHEN I T IS IN OUTPUT MODE AND WHEN A BUS THERMINAL IS FLOATING (HIGH IMPEDANCE STATE) IT IS REQUESTED TO F IX THE INPUT LEVEL BY BEANS OF EXTERNAL PULL DOWN OR PULL UP RESISTOR.
DESCRIPTION The LVQ245 is a low voltage CMOS OCTAL BUS TRANSCEIVER (3-STATE) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology . It is ideal for low power and low noise 3.3V applications. It has better speed performance at 3.3V than 5V LSTTL family combined with the true CMOS low power consumption. PIN CONNECTION AND IEC LOGIC SYMBOLS
February 1997
1/8
LVQ245
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
P IN No 1 2, 3, 4, 5, 6, 7, 8, 9 18, 17, 16, 15, 14, 13, 12, 11 19 10 20 S YMB O L DIR A1 to A8 B1 to B8 N AM E A ND F UNC T I O N Direc tional C ontro l Dat a In puts/ O utputs Dat a In puts/ O utputs
G GND VCC
Out put En abel In put Grou nd (0V) Pos it ive Su pply Vo lt age
TRUTH TABLE
I N P UT G L L H
X: "H" or "L" Z: High impedance
F UNC T I O N DI R L H X A BUS OUTPUT INPUT Z B BU S INPUT OUTPUT Z
O UT P UT A= B B= A Z
ABSOLUTE MAXIMUM RATINGS
S y mb o l VCC VI VO II K IOK IO Tstg TL Supply Vo lt age DC In put Volta ge DC Ou tpu t Vo lt age DC In put Diode Curr ent DC Ou tpu t D iode C u rrent DC Ou tpu t C urrent Stor age T emperat ur e Lead T empe ratu re (10 se c) P arame t er V al u e -0.5 to +7 -0.5 t o VCC + 0.5 -0.5 t o VCC + 0.5 ± 20 ± 20 ± 50 ± 400 -65 to +150 300 Un i t V V V mA mA mA mA
o o
ICC or IGND DC VCC or Gro und Current
C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. (*) 500mW: 65 oC derated to 300 mW by 10 mW/oC: 65 oC to 85 oC
RECOMMENDED OPERATING CONDITIONS
S y mb o l VCC VI VO Top tr, tf Inp ut Volta ge Out put V oltage Ope rat ing T empe ratu re : Inp ut Rise a nd Fa ll T im e ( VCC = 3V) ( note 2) P arame t er Supply Vo lt age ( note 1) Va lu e 2 to 3.6 0 to VCC 0 to VCC -40 to +85 0 to 10 Un i t V V V
o
C
ns/V
1) Truth Table guaranteed: 1.2V to 3.6V
2/8
LVQ245
DC SPECIFICATIONS
S ym b o l P ar am e te r V CC (V) VIH VIL VOH High Level I nput V o ltage Low L evel Input Volta ge High Level O ut put Volt age Low L evel Outp ut Volt age Input Leakage C urrent 3 St a te O utp ut L e akage Current Quies cent Supply Current Dynam ic Out put Current (not e 1 , 2) 3. 0 t o 3. 6 3.0 VO = 0.1 V or VCC - 0.1 V VI = V IH o r VIL VI = VIH or VIL
(*) (*)
T e st Co n d i t i o n s
o
Va lu e T A = 25 C Mi n. 2.0 0.8 2.9 2.58 0.002 0 0.1 0.36 ±0.1 ±0.3 4 36 -25 2.99 2.9 2.48 2.2 0.1 0.44 0.55 ±1 ±3 40 Typ. M a x. - 40 t o 85 C Min . 2.0 0.8 M ax.
o
Unit
V V V
I O= - 50 µ A IO= -12 mA IO= -24 mA IO=50 µA IO= 12 mA IO= 24 mA
VOL
3.0
V µA µA µA mA mA
II IOZ ICC IOLD IOHD
3. 6 3. 6 3.6 3.6
VI = VCC or GND VI = VIH or VIL VO = VCC or GND VI = VCC or GND VOLD = 0.8 V max VOHD = 2 V min
1) Maximum test duration 2ms, one output loaded at time 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 75 . (*) All outputs loaded.
DYNAMIC SWITCHING CHARACTERISTICS
S ym b o l P ar am e te r V CC (V) VOLP VOLV VIH D VILD Dynam ic Low V oltag e Quiet O utput ( note 1, 2) Dynam ic High Vo lt age Input (note 1 , 3) Dynam ic Low V oltag e Input (note 1 , 3) 3.3 -0.8 3.3 3.3 C L = 50 p F 0.8 T e st Co n d i t i o n s Mi n. Typ. 0.5 -0.5 2 V Va lu e T A = 2 5 oC M a x. 0.8 - 40 t o 85 o C Min . M ax. Unit
1) Worst case package 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n -1) outputs switching and one output at GND 3) max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD). f=1MHz
3/8
LVQ245
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 , Input tr = t f =3 ns)
S ym b o l P a r a m e te r V CC (V) tPLH tPHL tPZL tPZH tPLZ tPHZ tOSLZ tOSHL Propagati on D e lay T ime Out put En able Ti m e Out put D isable T im e Out put to Ou tp ut Sk ew Tim e (n ote 1 , 2) 2.7 3.3
(*)
T est C o n d i t i o n
o
Va lue - 40 t o 85 C T A = 25 C M i n . T y p . M a x. M i n . M ax. 7.5 14.0 15.0 6.0 9.5 7.5 10 7.5 0.5 0.5 10.0 18.0 13.0 20.0 14.5 1.0 1.0 10.5 19.0 13.5 21.0 15.0 1.5 1.5
o
Unit
ns ns ns ns
2.7 3.3(*) 2.7 3.3(*) 2.7 3.3
(*)
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW 2) Parameter guaranteed by design (*) Voltage range is 3.3V ± 0.3V
CAPACITIVE CHARACTERISTICS
S ym b o l P ar am e te r V CC (V) CIN C i/o C PD Input Capacita nce Input /Out p ut Capacita nc e Power D is sipat ion Capacit ance (n ote 1) 3. 3 3. 3 3.3 T e st Co n d i t i o n s Mi n. Typ. 5 10 16 Va lu e T A = 2 5 oC M a x. - 40 t o 85 o C Min . M ax. pF pF pF Unit
1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD · VCC · fIN + ICC/n (per circuit)
TEST CIRCUIT
T E ST t PLH, tPHL t PZL, tPL Z t PZH, tPHZ
CL = 50 pF or equivalent (includes jig and probe capacitance) RL = R1 = 500 or equivalent RT = ZOUT of pulse generator (typically 50)
SW I T C H Open 2VCC Open
4/8
LVQ245
WAVEFORM 1: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f =1MHz; 50% duty cycle)
5/8
Others parts begin by 74
74-1 74-2 74-3 74-4 74-5 74-6 74-7 74-8 74-9 74-10 74-11 74-12 74-13 74-14 74-15 74-16 74-17 74-18 74-19 74-20 74-21 74-22 74-23 74-24 74-25 74-26 74-27 74-28 74-29 74-30 74-31 74-32 74-33 74-34 74-35 74-36 74-37 74-38 74-39 74-40 74-41 74-42 74-43 74-44 74-45 74-46 74-47 74-48 74-49 74-50 74-51 74-52 74-53 74-54 74-55 74-56 74-57 74-58 74-59 74-60 74-61 74-62
|
|
|
