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Part: 74LVQ273T
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Datasheet: Download 74LVQ273T datasheet File size : 143 kB
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74LVQ273
OCTAL D-TYPE FLIP FLOP WITH CLEAR
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HIGH SPEED: fMAX = 150 MHz (TYP.) at VCC = 3.3V INPUT & OUTPUT TTL COMPATIBLE LEVELS LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA = 25 oC LOW NOISE: VOLP = 0.4 V (TYP.) at VCC = 3.3V 75 TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 12 mA (MIN) PCI BUS LEVELS GUARANTEED AT 24mA BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 273 IMPROVED LATCH-UP IMMUNITY
M (Micro Package)
T (TSSOP Package)
ORDER CODES : 74LVQ27 3M 74LVQ273 T Information signals applied to D inputs are transfered to the Q output on the positive going edge of the clock pulse. When the CLEAR inputs is held low, th e Q outputs are held low independ entely of the other inputs . It has better speed performance at 3 .3V than 5V LS-TTL family combined with the true CMOS low power consumption. All inputs and outputs are equipped with protection circuits against s tatic discharge, giving them 2KV ESD immunity and transient excess voltage.
DESCRIPTION The LVQ273 is a low voltage CMOS OCTAL D-TYPE FLIP FLOP WITH CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications.
PIN CONNECTION AND IEC LOGIC SYMBOLS
February 1997
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74LVQ273
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
P IN No 1 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 11 S YMB O L CLEAR Q0 to Q7 N AM E A ND F UNC T I O N Asy nc ronous Mas t e Res et (Act iv e LOW ) Flip-Flo p O ut pus
D0 to D7
Dat a In puts
CLOCK
Clock I nput (LOW - to-H I GH, EdgeTrig gered) Grou nd (0V) Pos it ive Su pply Vo lt age
10 20
GND VCC
TRUTH TABLE
I NP UT S CL E AR L H H H
X: Don't Care
O UT P UT S CLOCK X Q L L H Qn
F UN CT I O N CLEAR
D X L H X
NO CHANGE
LOGIC DIAGRAMS
This logic diagram has not be used to esimate propagation delays
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74LVQ273
ABSOLUTE MAXIMUM RATINGS
S y mb o l VCC VI VO II K IOK IO Tstg TL Supply Vo lt age DC In put Volta ge DC Ou tpu t Vo lt age DC In put Diode Curr ent DC Ou tpu t D iode C u rrent DC Ou tpu t C urrent Stor age T emperat ur e Lead T empe ratu re (10 se c) P arame t er V al u e -0.5 to +7 -0.5 t o VCC + 0.5 -0.5 t o VCC + 0.5 ± 20 ± 20 ± 50 ± 400 -65 to +150 300 Un i t V V V mA mA mA mA
o o
ICC or IGND DC VCC or Gro und Current
C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
RECOMMENDED OPERATING CONDITIONS
S y mb o l VCC VI VO Top dt/dv Inp ut Volta ge Out put V oltage Ope rat ing T empe ratu re : Inp ut Rise a nd Fa ll T im e ( VCC = 3V) ( note 2) P arame t er Supply Vo lt age ( note 1) Va lu e 2 to 3.6 0 to VCC 0 to VCC -40 to +85 0 to 10 Un i t V V V
o
C
ns/V
1) Truth Table guaranteed: 1.2V to 3.6V
3/10
74LVQ273
DC SPECIFICATIONS
S ym b o l P ar am e te r V CC (V) VIH VIL VOH High Level I nput V o ltage Low L evel Input Volta ge High Level O ut put Volt age Low L evel Outp ut Volt age Input Leakage C urrent Quies cent Supply Current Dynam ic Out put Current (not e 1 , 2) 3. 0 t o 3. 6 3.0 VI = V IH o r VIL VI = VIH or VIL
(*) (*)
T e st Co n d i t i o n s
o
Va lu e T A = 25 C Mi n. 2.0 0.8 Typ. M a x. - 40 t o 85 C Min . 2.0 0.8 2.9 2.48 2.2 0.002 0 0.1 0.36 ±0.1 4 36 -25 0.1 0.44 0.55 ±1 40 2.99 M ax.
o
Unit
V V V
I O= - 50 µ A IO= -12 mA IO= -24 mA IO=50 µA IO= 12 mA IO= 24 mA
2.9 2.58
VOL
3.0
V µA µA mA mA
II ICC IOLD IOHD
3. 6 3.6 3.6
VI = VCC or GND VI = VCC or GND VOLD = 0.8 V max VOHD = 2 V min
1) Maximum test duration 2ms, one output loaded at time 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50 .
DYNAMIC SWITCHING CHARACTERISTICS
S ym b o l P ar am e te r V CC (V) VOLP VOLV VIH D VILD Dynam ic Low V oltag e Quiet O utput ( note 1, 2) Dynam ic High Vo lt age Input (note 1 , 3) Dynam ic Low V oltag e Input (note 1 , 3) 3.3 -0.8 3.3 3.3 C L = 50 p F 0.8 T e st Co n d i t i o n s Mi n. Typ. 0.4 -0.5 2 V Va lu e T A = 2 5 oC M a x. 0.8 - 40 t o 85 o C Min . M ax. Unit
1) Worst case package 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n -1) outputs switching and one output at GND 3) max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD). f=1MHz
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74LVQ273
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 , Input tr = t f =3 ns)
S ym b o l P a r a m e te r V CC (V) tPLH tPHL tPHL twL tw tsL tsH thL thH tREM fMAX tOSLZ tOSHL Propagati on D e lay T ime CK to Q Propagati on D e lay T ime CLR t o Q CLR p ulse Wid th , H IGH CK pulse W idth Setu p T ime Q to C K HIG H o r LO W Hold Ti me Q to CK HIG H o r LO W Recov ery T im e CLR t o Q Max im um C lock Freq uency Out put to Ou tp ut Sk ew Tim e (n ote 1 , 2) 2.7 3.3
(*)
T est C o n d i t i o n
o
Va lue - 40 t o 85 C T A = 25 C M i n . T y p . M a x. M i n . M ax. 7.5 17.0 20.0 6.0 10.0 9.0 2.5 2.0 2.0 1.5 -0.4 -0.3 0.4 0.3 -0.1 0.0 60 90 150 190 0.5 0.5 1.0 1.0 12.0 18.0 13.0 7.0 5.5 7.0 5.5 6.5 5.0 3.0 2.0 5.0 4.0 50 70 1.5 1.5 14.0 20.0 14.0 8.5 6.0 8.5 6.0 8.5 6.0 3.5 2.5 6.5 4.5
o
Unit
ns ns ns ns ns ns ns M Hz ns
2.7 3.3(*) 2.7 3.3
(*)
2.7 3.3(*) 2.7 3.3
(*)
2.7 3.3(*) 2.7 3.3
(*)
2.7 3.3(*) 2.7 3.3
(*)
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW 2) Parameter guaranteed by design (*) Voltage range is 3.3V ± 0.3V
CAPACITIVE CHARACTERISTICS
S ym b o l P ar am e te r V CC (V) CIN C PD Input Capacita nce Power D is sipat ion Capacit ance (n ote 1) 3. 3 3.3 fIN = 10 MHz T e st Co n d i t i o n s
o
Va lu e T A = 25 C Mi n. Typ. 5 30 M a x. - 40 t o 85 C Min . M ax.
o
Unit
pF pF
1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD · VCC · fIN + ICC/n (per circuit)
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