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Part: 74LVT573PWDH
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Datasheet: Download 74LVT573PWDH datasheet File size : 110 kB
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INTEGRATED CIRCUITS
74LVT573 3.3V Octal D-type transparent latch (3-State)
Product specification Supersedes data of 1995 Nov 14 IC23 Data Handbook 1998 Feb 19
Philips Semiconductors
Philips Semiconductors
Product specification
3.3V Octal D-type transparent latch (3-State)
74LVT573
FEATURES
· Inputs and outputs on opposite side of package allow easy
interface to microprocessors
DESCRIPTION
The LVT573 is a high-performance BiCMOS product designed for VCC operation at 3.3V. This device is an octal transparent latch coupled to eight 3-State output buffers. The two sections of the device are controlled independently by Enable (E) and Output Enable (OE) control gates. The 74LVT573 has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocessors. The data on the D inputs are transferred to the latch outputs when the Latch Enable (E) input is High. The latch remains transparent to the data inputs while E is High, and stores the data that is present one setup time before the High-to-Low enable transition. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active-Low Output Enable (OE) controls all eight 3-State buffers independent of the latch operation. When OE is Low, the latched or transparent data appears at the outputs. When OE is High, the outputs are in the High-impedance "OFF" state, which means they will neither drive nor load the bus.
· 3-State output buffers · Common output enable · TTL input and output switching levels · Input and output interface capability to systems at 5V supply · Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
· Live insertion/extraction permitted · No bus current loading when output is tied to 5V bus · Latch-up protection exceeds 500mA per JEDEC Std 17 · Power-up 3-State · Power-up reset · ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
QUICK REFERENCE DATA
SYMBOL tPLH tPHL CIN COUT ICCZ PARAMETER Propagation delay Dn to Qn Input capacitance Output capacitance Total supply current CONDITIONS Tamb = 25°C; GND = 0V CL = 50pF; VCC = 3.3V VI = 0V or 3.0V Outputs disabled; VO = 0V or 3.0V Outputs disabled; VCC = 3.6V TYPICAL 2.5 2.7 4 8 .13 UNIT ns pF pF mA
ORDERING INFORMATION
PACKAGES 20-Pin Plastic SOL 20-Pin Plastic SSOP Type II 20-Pin Plastic TSSOP Type I TEMPERATURE RANGE 40°C to +85°C 40°C to +85°C 40°C to +85°C OUTSIDE NORTH AMERICA 74LVT573 D 74LVT573 DB 74LVT573 PW NORTH AMERICA 74LVT573 D 74LVT573 DB 74LVT573PW DH DWG NUMBER SOT163-1 SOT339-1 SOT360-1
PIN CONFIGURATION
PIN DESCRIPTION
PIN NUMBER 1 SYMBOL OE D0-D7 Q0-Q7 E GND VCC FUNCTION Output enable input (active-Low) Data inputs Data outputs Enable input (active-High) Ground (0V) Positive supply voltage
OE D0 D1 D2 D3 D4 D5 D6 D7
1 2 3 4 5 6 7 8 9
20 VCC 19 Q0 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 13 Q6 12 Q7 11 E
2, 3, 4, 5, 6, 7, 8, 9 19, 18, 17, 16, 15, 14, 13, 12 11 10 20
GND 10
SV00031
1998 Feb 19
2
8531750 18988
Philips Semiconductors
Product specification
3.3V Octal D-type transparent latch (3-State)
74LVT573
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
1 11 C1
EN
2
3
4
5
6
7
8
9 2 1D 19 18 17 16 15 14 13 12
D0 11 E
D1
D2 D3
D4
D5
D6
D7
3 4 5 6
1
OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
7 19 18 17 16 15 14 13 12 8 9
SV00032
SV00033
FUNCTION TABLE
INPUTS OE L L L L L H= h= L= l= NC = X= Z= = E H H L Dn L H I h X INTERNAL REGISTER L H L H NC OUTPUTS Q0 Q7 L H L H NC Z OPERATING MODE MODE
Enable and read register Latch and read register Hold Disable outputs
H X X NC High voltage level High voltage level one set-up time prior to the High-to-Low E transition Low voltage level Low voltage level one set-up time prior to the High-to-Low E transition No change Don't care High impedance "off" state High-to-Low E transition
LOGIC DIAGRAM
D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9
D
D
D
D
D
D
D
D
E
Q
E
Q
E
Q
E
Q
E
Q
E
Q
E
Q
E
Q
11 E 1 OE 19 Q0 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 13 Q6 12 Q7
SV00034
1998 Feb 19
3
Philips Semiconductors
Product specification
3.3V Octal D-type transparent latch (3-State)
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL VCC IIK VI IOK VOUT IOUT Tstg PARAMETER DC supply voltage DC input diode current DC input voltage3 DC output diode current DC output voltage3 DC output current output current Output in High state Storage temperature range 64 65 to 150 VO < 0 Output in Off or High state Output in Low state VI < 0 CONDITIONS RATING 0.5 to +4.6 50 0.5 to +7.0 50 0.5 to +7.0 128
74LVT573
UNIT V mA V mA V mA °C
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC VI VIH VIL IOH IOL t/v Tamb DC supply voltage Input voltage High-level input voltage Input voltage High-level output current Low-level output current Low-level output current; current duty cycle 50%, f 1kHz Input transition rise or fall rate; outputs enabled Operating free-air temperature range 40 PARAMETER MIN 2.7 0 2.0 0.8 32 32 mA 64 10 +85 ns/V °C MAX 3.6 5.5 V V V V mA UNIT
1998 Feb 19
4
Philips Semiconductors
Product specification
3.3V Octal D-type transparent latch (3-State)
74LVT573
DC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C MIN VIK Input clamp voltage VCC = 2.7V; IIK = 18mA VCC = 2.7 to 3.6V; IOH = 100µA VOH High-level output voltage VCC = 2.7V; IOH = 8mA VCC = 3.0V; IOH = 32mA VCC = 2.7V; IOL = 100µA VCC = 2.7V; IOL = 24mA VOL Low-level output voltage VCC = 3.0V; IOL = 16mA VCC = 3.0V; IOL = 32mA VCC = 3.0V; IOL = 64mA VRST Power-up output low voltage5 VCC = 3.6V; IO = 1mA; VI = GND or VCC VCC = 0 or 3.6V; VI = 5.5V II Input l k leakage current t VCC = 3.6V; VI = VCC or GND VCC = 3.6V; VI = VCC VCC = 3.6V; VI = 0 IOFF IHOLD Output off current Bus Hold current A inputs7 Current into an output in the High state when VO > VCC Power up/down 3-State output current3 3-State output High current 3-State output Low current VCC = 0V; VI or VO = 0 to 4.5V VCC = 3V; VI = 0.8V VCC = 3V; VI = 2.0V VCC = 0V to 3.6V; VCC = 3.6V IEX IPU/PD IOZH IOZL ICCH ICCL ICCZ ICC Additional supply current per input pin2 Quiescent supply current VO = 5.5V; VCC = 3.0V VCC 1.2V; VO = 0.5V to VCC; VI = GND or VCC; OE/OE = Don't care VCC= 3.6V; VO = 3V; VI = VIL or VIH VCC= 3.6V; VO = 0.5V; VI = VIL or VIH VCC = 3.6V; Outputs High, VI = GND or VCC, IO = 0 VCC = 3.6V; Outputs Low, VI = GND or VCC, IO = 0 VCC = 3.6V; Outputs Disabled; VI = GND or VCC, IO = 05 VCC = 3V to 3.6V; One input at VCC-0.6V, Other inputs at VCC or GND 75 75 ±500 60 1 1 1 0.13 3 0.13 0.1 125 ±100 5 5 0.19 12 0.19 0.2 mA mA µA µA µA Control pins Data pins pins4 VCC-0.2 2.4 2.0 TYP1 0.9 VCC-0.1 2.5 2.2 0.1 0.3 0.25 0.3 0.4 0.13 1 ±0.1 0.1 1 1 150 150 µA 0.2 0.5 0.4 0.5 0.55 0.55 10 ±1 1 -5 ±100 µA µA V V V MAX 1.2 V UNIT
NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. 2. This is the increase in supply current for each input at the specified voltage level other than VCC or GND 3. This parameter is valid for any VCC between 0V and 1.2V with a transition time of up to 10msec. From VCC = 1.2V to VCC = 3.3V ± 0.3V a transition time of 100µsec is permitted. This parameter is valid for Tamb = 25°C only 4. Unused pins at VCC or GND. 5. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 6. ICCZ is measured with outputs pulled to VCC or GND. 7. This is the bus hold overdrive current required to force the input to the opposite logic state.
1998 Feb 19
5
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