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Part: 75003177
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Programmable Media Processor
TriMedia TM-1100
O n a s i n g l e c h i p , a Tr i M e d i a TM T M - 1 1 0 0 d e l i v e r s real-time processing of audio, video, graphics, and communications datastreams. With its lowcost 133-MHz CPU and a full complement of on-chip I/O and coprocessing peripheral units, the TM-1100 media processor delivers up to 5.3 BOPS to new multimedia products. 100% pin compatibility with the TM-1000 processor ensures that developers can take immediate advantage of up to 33% more processing power in their existing TM-1000 designs. Comparable in programmability to a generalp u r p o s e p r o c e s s o r , t h e Tr i M e d i a T M - 1 1 0 0 architecture enables development of multimedia applications entirely in the C and C++ programming languages. Programmability improves time-to-market, lowers development costs, and extends product life through s o f t w a r e u p g r a d a b i l i t y. MULTIMEDIA APPLICATIONS The TM-1100 is an ideal building block for any multimedia application that processes multiple multimedia and communications datastreams. It is well suited for creating a range of consumer and professional products such as videophones, videoconferencing and video editing systems, security systems, DVD encode/decode devices, and digital television appliances. SINGLE-CHIP MULTIMEDIA ENGINE Powered by a low-cost, 133-MHz, C-programmable CPU, the TriMedia TM-1100 strikes a perfect compromise between cost and performance. To streamline data throughput, TM-1100 incorporates independent on-chip DMA-driven peripheral units that manage datastream I/O and formatting and accelerate processing of key multimedia algorithms. To reap the full benefit of the CPU and processing units, TM-1100's sophisticated memory hierarchy manages internal I/O and streamlines access to external memory. The result -- a single, low-cost programmable chip that powers standalone and PC-hosted multimedia products.
FEATURES
+ Processes audio, video, graphics and communications datastreams on a single chip + Powerful, fine-grain parallel, 133-MHz VLIW CPU with versatile instruction set includes special multimedia and DSP operations + Pin compatibility with TM-1000 delivers up to 33% more performance to TriMedia TM-1000 designs + Multiple, independent, DMA-driven multimedia I/O and coprocessing units format data and offload the CPU + Enhanced video out functionality includes 7-bit alpha blending, full chroma keying, genlock capability, and programmable YUV color clipping + PCI/XIO bus interface supports glueless interface to a mix of PCI and 8-bit microcomputer peripheral chips, such as ROM/Flash, EEPROM, 68K, and x86 devices + Robust software development tools enable multimedia application development entirely in C/C++ + DVD playback authentication/descrambling functions for PC and standalone applications + 16- and 64-Mbit SDRAM support up to 133-MHz
SDRAM
M A I N MEMORY INTERFACE
V I D E O IN
V L D COPROCESSOR
A single-chip multimedia engine
Powered by a low-cost, 133-MHz, C-programmable CPU, the TriMedia TM-1100 strikes a perfect compromise between cost and performance.
A U D I O IN
E N H A N C E D VIDEO OUT
A U D I O OUT
TIMERS
I 2 C INTERFACE
SYNCHRONOUS S E R I A L INTERFACE
INSTR. CACHE V L I W CPU DATA CACHE
IMAGE COPROCESSOR
P C I / X I O INTERFACE
TO PCI/XIO BUS
INTERNAL BUS (DATA HIGHWAY)
T M - 1 1 0 0 ARCHITECTURE O n a single chip, t h e TM-1100 incorporates a powerful CPU and p e r i p h e r a l s to accelerate processing of audio, v i d e o , g r a p h i c s , a n d c o m m u n i c a t i o n s data.
PROGRAMMABLE VLIW CPU The TM-1100 delivers top performance through an elegant implementation of a very-long instruction word (VLIW) architecture. Key to the TriMedia processor's VLIW implementation, parallelism is optimized at compile time by the TriMedia compilation system. No specialized scheduling hardware is required to parallelize code during execution. Hardware saved by eliminating complex scheduling logic reduces cost and allows the integration of multimedia features that enhance the power of the CPU in multimedia applications. The TM-1100 processor's powerful DSP-like, 32-bit CPU achieves fine-grain parallelism by simultaneously targeting five of its 27 pipelined functional units within one clock cycle. Most common operations have their results available in one clock cycle; more complex operations have multicycle latencies. Functional units can access 128 fully general-purpose, 32-bit registers during execution. Since registers are not separated into banks, any operation can use any register for any operand. Both big and little endian byte ordering are supported. The TriMedia TM-1100 CPU also provides special support for instruction and data breakpoints, useful in debugging and program development.
POWERFUL, DSP-LIKE, C-CALLABLE MULTIMEDIA OPS In addition to traditional microprocessor operations and a full complement of 32-bit, IEEE-compliant, floating point operations, the TM-1100 instruction set includes multimedia and DSP operations that accelerate the performance of multimedia applications. Such multimedia operations can replace up to 11 traditional microprocessor operations. When incorporated into application source code, they dramatically improve performance and amplify the efficiency of the TM-1100's parallel architecture. Multimedia operations are invoked with familiar function-call syntax consistent with the C programming language. They are automatically scheduled to take full advantage of the TriMedia processor's highly parallel VLIW implementation. As with all other operations generated by the TriMedia VLIW compilation system, the scheduler takes care of register allocation, operation packing, and flow analysis. The TM-1100 processor enhances the multimedia operation set available for the TM-1000 with 6 additional operations that improve efficiency of MPEG-2 9-bit precise decoding, support video de-interlacing (median filtering), and more. MEMORY SYSTEM OVERVIEW To reap the full benefit of the TM-1100 processor's CPU and processing units, its memory hierarchy must read and write data (and instructions) fast enough to keep these units busy. Thus to meet the
TM-1100 Specifications
PHYSICAL Process Packaging Pins Power CACHES Access Associativity Block Size Size
C75: CMOS 0.35 micron; 5-layer metal TE_QFP total 240 I/O pins 3.3 V with 5 V tolerance supply 3.3 V +/- 5% dissipation 6W (max) consumption 1808 mA 5.97 W management dynamic standby less than 990 mW
data 8-, 16-, 32-bit word instruction 64 bytes 8-way set-associative with LRU replacement 64 bytes data 16 KB instruction 32 KB
INTERNAL DATA HIGHWAY Protocol 64-byte block-transfer separate 32-bit data and 32-bit address buses PCI INTERFACE Speed Bus Width Address Space Voltage Standard Compliance VIDEO IN Supported Signals Image Sizes Functions
CENTRAL PROCESSING UNIT Clock Speed 133 MHz Instruction Length Instruction Set variable (2 to 23 bytes); compressed arithmetic and logical ops, load/store ops., special multimedia and DSP ops., IEEE-compliant floating point ops. 5 27, pipelined integer and floating-point arithmetic units, data-parallel DSP-like units name quantity latency recovery constant 5 1 1 integer ALU 5 1 1 memory load/store 2 3 1 shift 2 1 1 DSPALU 2 2 1 DSP multiply 2 3 1 branch 3 3 1 float ALU 2 3 1 integer/float mul 2 3 1 float compare 1 1 1 float sqrt./divide 1 17 16 Registers Special Multimedia/ DSP Operations MEMORY SYSTEM Speed CPU/Memory Speed Ratios Memory Size Supported Types Width Max. Bandwidth Interface 128 (32-bit width) total 32 ops
33 MHz 32-bit 32 bits (4 GB) drive and receive at 3.3V or 5V PCI Local Bus Specification 2.1
Issue Slots Functional Units
CCIR 601/656 8-bit video up to 19 Mpix/sec raw 8-10-bit data (messages) up to 38 MB/sec all sizes, subject to sample rate programmable on-the-fly 2X horizontal resolution subsampling
ENHANCED VIDEO OUT Image Sizes flexible, including CCIR601; maximum 4K x 4K pixels (subject to 80 MB/sec data rate) Input Formats Output Formats Clock Rates Transfer Speeds YUV 4:2:2, YUV 4:2:0 CCIR601/656 8-bit video, PAL or NTSC programmable (4-80 MHz), typically 27 MB/sec (13.5 Mpixels/sec for NTSC, PAL) 80 MB/sec in data-streaming and message-passing modes; 40 Mpix/sec in YUV 4:2:2 mode full 129-level alpha blending, genlock mode, frame synchronization, chroma key, programmable YUV color clipping
66/80/100/133 MHz programmable; 1:1, 5:4, 4:3, 3:2, and 2:1 512 KB to 64 MB (up to four ranks) 16-Mbit SDRAM (x4, x8, x16); SGRAM (x32); 64-Mbit SDRAM (x32) 32-bit bus 532 MB/sec (at 133 MHz) glueless up to 4 16-Mbit or 2 64-Mbit chips at 133 MHz; more chips with slower clock and/or external buffers 3.3 V LVTTL
Functions
AUDIO IN / AUDIO OUT Number of Channels 2 input; 8 output Sample Size Sample Rates Data Formats External Interface 8- or 16-bit samples per channel 1 Hz to 100 KHz programmable with 0.001 Hz resolution 8-bit mono and stereo; 16-bit mono and stereo PC standard memory data format 4 pins each: 1 programmable clock output, 3 flexible serial input (AI) or output (AO) interface internal or external I2S and other serial 3-wire protocols
Signal Levels
Clock Source Native Protocol
Multimedia application development entirely in C and C++
By enabling development of multimedia applications entirely in the C and C++ programming languages, the SDE dramatically lowers development costs, reduces time-to-market, and ensures code portability to next generation architecture.
ROBUST SOFTWARE DEVELOPMENT ENVIRONMENT The TriMedia software development environment (SDE) includes a full suite of system software tools to compile and debug code, analyze and optimize performance, and simulate execution for the TM-1100 processor. By enabling development of multimedia applications entirely in the C and C++ programming languages, the SDE dramatically lowers development costs, reduces time-to-market, and ensures code portability to next generation architecture. TRIMEDIA REAL-TIME OPERATING SYSTEM KERNELS For multimedia applications requiring system resource and task management, the TM-1100 media processor supports the pSOS+TM embedded real-time operating system kernels. Developed by Integrated Systems, Inc. (ISI), the pSOS+ kernels are optimized to deliver the deterministic response essential for multimedia applications.
internal I/O requirements of its target applications, the TM-1100 couples substantial on-chip caches with a glueless memory interface. Dedicated instruction and data cache -- TM-1100's CPU is
H O S T- A S S I S T E D COPROCESSOR
SDRAM
CAMERA
supported by separate, dedicated on-chip data and instruction caches. Even without a second-level cache structure, TriMedia caches deliver media performance an order of magnitude greater than x86 processors. The dual-ported data cache allows two simultaneous accesses. It is non-blocking, thus cache misses and CPU cache accesses can be handled simultaneously. Early restart techniques reduce read-miss latency. Background copyback reduces CPU stalls. To reduce internal bus bandwidth requirements, instructions in main memory and cache use a compressed format. The compressed instruction format improves the cache hit rate and reduces bus bandwidth. Instructions are compressed during compilation and decompressed in the instruction cache before being processed by the CPU. To improve cache behavior and thus performance, both caches have a locking mechanism. Cache coherency is maintained by software.
P C I / X I O BUS AUDIO CAMERA HOST CPU P C I / X I O BUS AUDIO
VCR T V MONITOR GRAPHICS CARD AUDIO
R G B IMAGE SEQUENCES
MEMORY
S TA N D A L O N E
SDRAM
VCR T V MONITOR PERIPHERAL PERIPHERAL
AUDIO
Glueless memory system interface -- TM-1100's glueless main memory interface couples the on-chip caches and multimedia peripheral units to main memory (SDRAM). It acts as the SDRAM controller and programmable central arbiter that allocates SDRAM memory bandwidth for on-chip peripheral unit activities. Higher
T M - 1 1 0 0 is designed for use as a coprocessor in a PC-hosted e n v i r o n m e n t or as the sole CPU in standalone systems.
ROM/FLASH BUS ARBITER
bandwidth SDRAM permits TM-1100 to use a narrower and simpler interface than would be required to achieve similar performance with standard DRAM. The TM-1100 memory interface provides sufficient capacity to drive
U M E 8 U U : SUM OF ABSOLUTE VALUES OF UNSIGNED 8-BIT DIFFERENCES
a memory system consisting of up to 133-MHz, 8-MB (four 2Mx8) or 16-MB (two 2Mx32) SDRAMs. Larger memories can be implemented by using lower memory system clock frequencies or external buffers. Programmable speed ratios allow SDRAM to have a different clock speed than the TM-1100 CPU. Support for a variety of memory types, speeds, bus widths, and off-chip bank sizes allow a range of
DSPALU FUNCTIONAL UNIT
S O U R C E REGISTER 1
31 0 31
S O U R C E REGISTER 2
0
A
B
C
D
E
F
G
H
|A-E|
+
|B-F|
+
|C-G|
+
|D-H|
TM-1100-based systems to be configured. HIGH-SPEED INTERNAL BUS (DATA HIGHWAY)
31
0
The memory system interface also mediates bandwidth allocation of
DESTINATION REGISTER
RESULT
the TM-1100's on-chip central data highway. A high-speed internal bus consisting of separate 32-bit address and data buses, the data highway connects the CPU and all on-chip I/O and coprocessing units to external SDRAM (through the memory interface) and to an off-chip PCI or XIO bus (through the PCI/XIO interface). Programmable bandwidth enables the data highway to deliver real-time responsiveness in a variety of multimedia applications.
S P E C I A L MULTIMEDIA OPERATIONS T h e ume8uu operation, c o m m o n l y used for motion estimation in video compression, i m p l e m e n t s 11 simple operations in one TriMedia special op.
Others parts begin by 75
75-1
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