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Part: 75006379
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Programmable Media Processor
TriMedia TM-1300
C o n t i n u i n g a tradition of high-performance, l ow - c o s t m e d i a processors, t h e TriMediaTM TM-1300 delivers up t o 66% more processing power 1 t o multimedia applicat i o n s at a lower unit cost. B y combining a 166-MHz C P U and a full complement of enhanced on-chip I/O a n d coprocessing units, T M - 1 3 0 0 achieves up to 6.5 bill i o n operations per second--ideal for applications r e q u i r i n g real-time processing of video, a u d i o, g r a p h i c s , a n d communications datastreams. T M - 1 3 0 0 boosts performance through a faster clock s p e e d and a faster main memory interface than previo u s TriMedia processors. D a t a s t r e a m I/O is enhanced w i t h a new on-chip unit for handling audio output in S o n y / P h i l i p s digital format (SPDIF). L ow e r power cons u m p t i o n and a smaller footprint contribute to making
FEATURES + Processes audio, video, graphics and communications datastreams on a single chip + Ideal for video-centric multimedia applications + Powerful, fine-grain parallel, 143- or 166-MHz VLIW CPU achieving up to 6.5 BOPS + Versatile instruction set includes traditional microprocessor, special multimedia SIMD, and IEEE floating-point operations + Comprehensive software development tools enable multimedia application development entirely in the C/C++ programming languages + On-chip, independent, DMA-driven multimedia I/O and coprocessing units offload the CPU + PCI/XIO host bus interface supports glueless interface to PCI and eight-bit microcomputer peripherals, including ROM/Flash, EEPROM, 68K, and x86 devices + 16- and 64-Mbit SDRAM support up to 143 MHz + On-chip DVD playback authentication/descrambling + TriMedia application libraries available from Philips and thirdparty suppliers provide solutions for MPEG-2 decode, Dolby Digital (AC-3)® decode, and more
t h e TM-1300 a more efficient and compact processing s o l u t i o n for new multimedia designs.
TM-1300 is an ideal building block for applications requiring simultaneous processing of several types of multimedia datastreams. With ample computational power available to capture, compress and decompress many video and audio data formats in real time, TM-1300 is well suited for a broad range of videocentric applications such as videoconferencing, video editing, video-based security, surveillance, or industrial inspection systems, and multifunctional devices such as digital TV sets and set-top boxes. It also supports applications in a JavaTM virtual machine environment. With its comprehensive software development environment, the TriMedia SDE, TM-1300 is comparable in ease of programmability to general-purpose processors. The SDE enables multimedia application development entirely in the C and C++ languages improving time-to-market and lowering product development and maintenance costs.
1
compared to TM-1000 processors
TriMedia TM-1300
System-on-a-chip multimedia engine
TRIMEDIA T M - 1 3 0 0 ARCHITECTURE O n a single chip, t h e TM-1300 incorporates a powerful CPU and p e r i p h e r a l s to accelerate processing of audio, v i d e o , g r a p h i c s , c o n t r o l , a n d communications datastreams.
T h e TriMedia TM-1300 strikes a perfect balance between c o s t and performance. A powerful C/C++-programmable V L I W CPU coordinates on-chip activities. To reap the full b e n e f i t of the CPU, i n d e p e n d e n t , o n - c h i p, b u s - m a s t e r i n g D M A peripheral units manage and format datastream I/O a n d accelerate processing of multimedia algorithms. A s o p h i s t i c a t e d memory hierarchy manages internal I/O and s t re a m l i n e s access to external memory. T h e result--a single, l ow - c o s t , p rog r a m m a b l e system-on-a-chip uniquely suited f o r both standalone and hosted multimedia products.
reduces cost and allows the integration of multimedia-specific features that enhance the power of the CPU. The TM-1300 CPU implements a 32-bit linear address space and 128 fully general-purpose 32-bit registers. Registers are not separated into banks enabling any operation to use any register for any operand. High-powered, DSP-like, C/C++-callable special operations--In addition to traditional microprocessor operations and a full complement of 32-bit, IEEE-compliant, floating point operations, the TM1300 instruction set includes special multimedia and DSP operations (ops) to accelerate the performance of SIMD (single instruction, multiple data) computations common in multimedia applications. These special ops combine multiple simple operations into a single VLIW instruction that can implement up to 12 traditional microprocessor operations in a single clock cycle. When incorporated into application source code, special ops dramatically improve performance and increase the efficiency of the TM-1300 parallel architecture. Special multimedia ops are invoked with familiar function-call syntax consistent with the C/C++ programming languages. They are automatically scheduled to take full advantage of the TriMedia processor's highly parallel VLIW implementation. As with all other operations generated by the TriMedia VLIW compilation system, the scheduler takes care of register allocation, operation packing, and flow analysis.
PROGRAMMABLE VLIW CPU A powerful DSP-like CPU delivers top performance through an elegant implementation of a fine-grain parallel, very-long instruction word (VLIW) architecture. Its five issue-slot instruction length enables up to five simultaneous operations to be scheduled into a single VLIW instruction. These operations can simultaneously target any five of the CPU's 27 pipelined functional units within one clock cycle. Most common operations have their results available in one clock cycle; more complex operations may have multicycle latencies. Unique to the TriMedia VLIW implementation, parallelism is optimized at compile time by an innovative compilation system. No specialized scheduling hardware is required to parallelize code during execution. Hardware saved by eliminating complex scheduling logic
ON-CHIP I/O AND COPROCESSING UNITS Video input--The video input (VI) unit reads digital video datastreams from an off-chip source into main memory. It accepts signals from any CCIR656-compliant device that outputs eight-bit parallel, 4:2:2 YUV time-multiplexed video data, such as a digital video camera, digital video decoder, or devices connected through ECL-level converters to the standard D1 parallel interface. After input, YUV data is demultiplexed, subsampled as needed, and written to SDRAM. The VI unit can also be programmed to perform on-the-fly 2X horizontal resolution subsampling enabling high-resolution images (720 pixels/line) to be converted to 360 pixels/line without loading the CPU. When low resolution video is desirable, subsampling during data capture reduces initial storage and bus bandwidth requirements. The VI unit can also receive raw data and unidirectional messages from another TM-1300 video out port. Video output--The video out (VO) unit outputs a digital YUV datastream to off-chip video subsystems such as a digital video encoder chip, digital video recorder, or other CCIR656-compatible device. The output signal is generated by gathering bytes from the separate Y, U, and V planes stored in SDRAM. While generating the multiplexed stream, the VO unit can perform programmed processing tasks, including horizontal 2X upscaling to convert from CIF/SIF to CCIR 601 resolution. For simultaneous display of graphics and live video, the VO unit can perform 129-level
alpha blending to generate sophisticated graphics overlays of arbitrary size and position within the output image. Chroma keying, genlock frame synchronization, programmable YUV output clipping are also
U M E 8 U U : SUM OF ABSOLUTE VALUES OF UNSIGNED 8-BIT DIFFERENCES
supported. The VO unit can also be used to pass raw data and unidirectional messages between TriMedia processors.
S O U R C E REGISTER 1
31 0 31
S O U R C E REGISTER 2
0
The VO unit can either supply or receive video clock and/or synchronizing signals from the external interface. Clock and timing registers can be precisely controlled through programmable registers. Programmable interrupts and dual buffers facilitate continuous data streaming by allowing the CPU to set up a buffer while another is being emptied by the VO unit. Audio input and output--The audio input (AI) and audio output
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B
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F
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|B-F|
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|C-G|
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|D-H|
DSPALU FUNCTIONAL UNIT
31
0
(AO) units provide all signals needed to read and write digital audio
DESTINATION REGISTER
RESULT
datastreams to/from most high-quality, low-cost serial audio oversampling A/D and D/A converters and codecs. Both units connect to offchip stereo converters through flexible bit-serial interfaces.
S P E C I A L MULTIMEDIA OPERATIONS T h e ume8uu operation, c o m m o n l y used for motion estimation in v i d e o compression, i m p l e m e n t s 11 simple operations in one Tr i M e d i a special op.
The AI and AO units are highly programmable providing tremendous flexibility in handling custom datastreams, adapting to custom protocols, and upgrading to future audio standards. Driven by TM-1300, the programmable audio sampling clock system supports a variety of sample rates with fine-grain resolution enabling audio and video synchronization in even the most complex multimedia applications.
filtering and scaling and can optionally perform YUV to RGB colorspace conversion for screen display (in memory-to-PCI mode). The ICP also provides display support for live video in occluded windows. The number and sizes of windows processed are limited only by available bandwidth. The final resampled and converted images are transmitted over the PCI bus to an optional off-chip graphics card/frame buffer. Variable length decoder--A variable length decoder (VLD) unit operates as a memory-to-memory coprocessor to decode Huffmanencoded MPEG-1 and MPEG-2 video datastreams. After processing, the VLD unit outputs a decoded stream optimized for MPEG-2 decompression software. This minimizes communications with the CPU where other steps of MPEG processing are performed. DVD descrambler--The on-chip digital versatile disc (DVD) descrambler unit provides DVD authentication and descrambling. This enables developers to add low-cost, flexible DVD video playback functions into multimedia products with minimal effort. I2C interface--An I2C interface provides an external I2C (or compatible interface) for use in hardware or software operation modes. In hardware mode, it can connect to and control a variety of different I2C multimedia devices allowing configuration and status inspection of off-chip peripheral video devices such as digital encoders and decoders, digital cameras, parallel I/O expanders, and more. I2C software mode enables full software control of the I2C interface. The interface can also be used to read the boot program from an off-chip EEPROM. The AI unit supports up to two channels of audio input. Mono and 16-bit stereo formats are supported. The AO unit delivers up to eight channels of output using one external pin per channel. Output of 16bit and 32-bit stereo and mono formats are supported. The AO unit can also be used to control highly integrated PC codecs. Software support for decode and output of Dolby ProLogic® and Dolby Digital (AC-3)® multichannel audio is provided through optional TriMedia application library modules. SPDIF output--The SPDIF out unit allows output of a one-bit high-speed serial datastream. The primary application is output of digital audio data in SPDIF format to external audio equipment. Since datastream content is entirely software controlled, the SPDIF out unit can also be used as a general purpose high-speed datastream output device such as a UART. The SPDIF out unit supports two-channel linear PCM audio, one or more Dolby Digital six-channel datastreams (embedded per Project 1937), or one or more MPEG-1 or MPEG-2 audio streams (embedded per Project 1937). It supports arbitrary, programmable sample rates independent of and asynchronous to the AO unit sample rate. Image coprocessor--The image coprocessor (ICP) unit off-loads the CPU of cycle-consuming image processing tasks such as copying an image from SDRAM to a host video frame buffer. The ICP unit can operate as either a memory-to-memory or memory-to-PCI coprocessor device. In both modes, it can perform horizontal or vertical image Synchronous serial interface--A synchronous serial interface (SSI) unit provides serial access for a variety of multimedia and data communications applications. It contains the buffers and logic necessary to interface with simple analog modem front ends. When used with a TriMedia V.34 application, the SSI unit can provide fully V.34-compliant modem capability. Alternatively, it can be connected to an ISDN interface chip to provide advanced digital modem capabilities. Timers--TM-1300 provides four general purpose timers useful in counting/timing events such as CPU clock cycles, data/instruction breakpoints, cache tracing, audio/video clocks, and more. Three timers are available to programmers, the fourth is reserved for use by system software. PCI/XIO bus interface--A PCI/XIO interface connects the CPU and on-chip peripheral units to a PCI/XIO bus. In embedded applications where TM-1300 is the main processor, this interface enables TM-1300 to access off-chip devices implementing functions not provided on-chip. In host-based applications, the interface connects TM1300 to a standard PCI bus, allowing placement directly on the host mainboard or a plug-in card. For low-cost standalone systems, XIO support allows glueless connection of eight-bit x86 or 68K devices such as ROM, Flash, EEPROM, UARTs, and more.
MEMORY SYSTEM OVERVIEW
To meet the performance requirements of its target applic a t i o n s while maintaining low cost, t h e TM-1300 memory s u b s y s t e m couples substantial on-chip caches with a gluel e s s memory interface through a unique internal bus or d a t a highway.
ROBUST SOFTWARE DEVELOPMENT ENVIRONMENT The TriMedia SDE includes a full suite of system software tools to compile and debug code, analyze and optimize performance, and simulate execution for the TM-1300 processor. The SDE dramatically lowers development costs, reduces time-to-market, and ensures code portability to next generation architecture by enabling development of multimedia applications entirely in the C and C++ programming languages. The TriMedia SDE Version 2.0 also supports Metrowerks® CodeWarrior® plug-ins. These plug-ins enable programmers to develop C code for TriMedia processors using the popular CodeWarrior Integrated Professional Development Environment (IDE). TRIMEDIA APPLICATION LIBRARIES Many TriMedia application libraries are available to accelerate product development of common standard-compliant software algorithms used in processing multimedia datastreams. These C-callable routines are optimized for top performance on the TriMedia architecture. Application libraries are available from Philips and third-party suppliers and include functions such as MPEG-1 encode or decode, MPEG2 MP@ML decode, MPEG-2 1/2D1 MP@ML encode, H.320, H.324, Dolby ProLogic or Dolby Digital (AC-3) decode, communications protocols, and many more. The TM-1300 can also support Java applications with third-party Java virtual machine environments.
Dedicated instruction and data cache--The TM-1300 CPU is supported by separate, dedicated on-chip data and instruction caches that employ a variety of techniques to improve cache hit ratios and thus CPU performance. The dual-ported data cache allows two simultaneous accesses. It is non-blocking thus cache misses and CPU cache accesses can be handled simultaneously. Early restart techniques reduce read-miss latency. Background copyback reduces CPU stalls. To reduce internal bus bandwidth requirements, instructions in main memory and cache use a compressed format. Instructions are decompressed in the instruction cache decompression unit before being processed by the CPU. To improve cache behavior and thus performance, both caches have a locking mechanism. Cache coherency is maintained by software. Glueless memory system interface--The TM-1300 couples main memory to substantial on-chip caches through a glueless main memory interface (MMI). The MMI acts as the main memory controller and programmable central arbiter that allocates memory bandwidth for on-chip peripheral unit activities. Support for a variety of memory configurations enables a wide variety of TM-1300-based systems to be built. The MMI supports 16-Mbit and 64-Mbit SDRAMs and provides sufficient drive capacity for an up to 143-MHz memory system comprising 8-MB (one 2Mx32), 16MB (two 4Mx16 or two 2Mx32), or 32-MB (four 4Mx16 or four 2Mx32) memories. Larger memories (up to 64 MB) can be implemented using lower memory system clock frequencies or external buffers. Higher bandwidth SDRAM permits TM-1300 to use a narrower and simpler interface than is required to achieve similar performance with standard DRAM. Programmable speed ratios allow SDRAM to have a different clock speed than the TM-1300 CPU. HIGH-SPEED INTERNAL BUS (DATA HIGHWAY) The TM-1300 CPU and processing units access external SDRAM through the on-chip internal bus or data highway comprising separate 32-bit address and data buses. Handled by the MMI, programmable bus arbitration enables the data highway to maintain real-time responsiveness in a variety of applications.
H O S T- A S S I S T E D C O P R O C E S S O R
SDRAM
C AMERA
VCR TV MONITOR GRAPHICS CARD
AUDIO
AUDIO
PCI/XIO BUS
RGB IMAGE SEQUENCES
HOST CPU
MEMORY
S TA N D A L O N E
SDRAM
C AMERA
VCR TV MONITOR PERIPHERAL PERIPHERAL
AUDIO
AUDIO
PCI/XIO BUS
RO M/FLASH
BU S ARBITER
T M - 1 3 0 0 is designed for use as the sole CPU in standalone systems a n d as a coprocessor in a hosted or multiprocessor environment.
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