|
|
Part: 80C451X
Category:
Description:
Company:
Datasheet: Download 80C451X datasheet File size : 1927 kB
Request For quote: Find where to buy 80C451X
Datasheet text preview:
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C451/83C451/87C451
DESCRIPTION
The Philips 8XC451 is an I/O expanded single-chip microcontroller fabricated with Philips high-density CMOS technology. Philips epitaxial substrate minimizes latch-up sensitivity. The 8XC451 (includes the 80C451, 87C451 and 83C451) is a functional extension of the 87C51 microcontroller with three additional I/O ports and four I/O control lines for a total of 68 pins. Four control lines associated with port 6 facilitate high-speed asynchronous I/O functions. The 8XC451 includes a 4k × 8 ROM (83C451) EPROM (87C451), a 128 × 8 RAM, 56 I/O, two 16-bit timer/counters, a five source, two priority level, nested interrupt structure, a serial I/O port for either a full duplex UART, I/O expansion, or multi-processor communications, and on-chip oscillator and clock circuits. The 80C451 ROMless version includes all of the 83C451 features except the on-board 4k × 8 ROM. The 87C451 has 4k of EPROM on-chip as program memory and is otherwise identical to the 83C451. The 8XC451 has two software selectable modes of reduced activity for further power reduction; idle mode and power-down mode. Idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. Power-down mode freezes the oscillator, causing all other chip functions to be inoperative while maintaining the RAM contents.
PIN CONFIGURATION
9 1 61
10
60
LCC
26
44
27 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Function EA/VPP P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC P4.7 P4.6 P4.5 P4.4 P4.3 Pin 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Function P4.2 P4.1 P4.0 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD P5.0 P5.1 P5.2
43 Pin 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Function P5.3 P5.4 P5.5 P5.6 P5.7 XTAL2 XTAL1 V SS ODS IDS BFLAG AFLAG P6.0 P6.1 P6.2 P6.3 P6.4 P6.5 P6.6 P6.7 PSEN ALE/PROG
FEATURES
· 80C51 based architecture · Seven 8-bit I/O ports · Port 6 features:
Eight data pins Four control pins Direct MPU bus interface Parallel printer interface
SU00084A
· On the microcontroller:
4k × 8 ROM (83C451) 4k × 8 EPROM (87C451) ROMless version (80C451) 128 × 8 RAM Two 16-bit counter/timers Two external interrupts
· External memory addressing capability
64k ROM and 64k RAM
· Low power consumption:
Normal operation: less than 24mA at 5V, 12MHz Idle mode Power-down mode
1996 Aug 16
3-292
8530830 17194
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C451/83C451/87C451
ORDERING INFORMATION
ROMless SC80C451CCA68 SC80C451CGA68 SC80C451ACA68 SC80C451AGA68 ROM SC83C451CCA68 SC83C451CGA68 SC83C451ACA68 SC83C451AGA68 EPROM1 SC87C451CCA68 SC87C451CGA68 SC87C451ACA68 SC87C451AGA68 SC87C451CGK68 NOTE: 1. OTP = One Time Programmable OTP OTP OTP OTP OTP TEMPERATURE RANGE °C AND PACKAGE 0 to +70, Plastic Leaded Chip Carrier, 0 to +70, Plastic Leaded Chip Carrier 40 to +85, Plastic Leaded Chip Carrier 40 to +85, Plastic Leaded Chip Carrier 0 to +70, Ceramic Leaded Chip Carrier FREQ MHz 3.5 to 12 3.5 to 16 3.5 to 12 3.5 to 16 3.5 to 16 DRAWING NUMBER SOT188-3 SOT188-3 SOT188-3 SOT188-3 1473A
LOGIC SYMBOL
V CC XTAL1 PORT 0 ADDRESS AND DATA BUS VS S
XTAL2
SECONDARY FUNCTIONS
RST EA/VPP PSEN ALE/PROG RxD TxD INT0 INT1 T0 T1 WR RD
PORT 3
PORT 2
PORT 1
ADDRESS BUS
PORT 6 CONTROL
ODS IDS BFLAG AFLAG
PORT 6
PORT 5
PORT 4
SU00085
1996 Aug 16
3-293
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C451/83C451/87C451
BLOCK DIAGRAM
P0.0P0.7 P2.0P2.7 P4.0P4.7 P5.05.7
PORT 0 DRIVERS V CC VS S RAM ADDR REGISTER RAM PORT 0 LATCH
PORT 2 DRIVERS
PORT 4 DRIVERS
PORT 5 DRIVERS
PORT 2 LATCH
PORT 4 LATCH
PORT 5 LATCH
4K x 8 ROM/EPROM
B REGISTER
ACC
STACK POINTER
TMP2
TMP1
PROGRAM ADDRESS REGISTER
BUFFER ALU PCON TL1 PSW SBUF IE IP INTERRUPT, SERIAL PORT AND TIMER BLOCKS PC INCREMENTER SCON TH0 TMOD TL0 TCON TH1
PROGRAM COUNTER PSEN ALE/PROG EAVPP RST PD TIMING AND CONTROL INSTRUCTION REGISTER
DPTR
PORT 1 LATCH
PORT 6 LATCH
PORT 3 LATCH
OSCILLATOR PORT 1 DRIVERS XTAL1 XTAL2 PORT 6 DRIVERS PORT 6 CONTROL/STATUS PORT 3 DRIVERS
P1.0P1.7
P6.0P6.7
IDS ODS BFLAG AFLAG
P3.0P3.7
SU00086
1996 Aug 16
3-294
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C451/83C451/87C451
PIN DESCRIPTION
MNEMONIC VSS VCC P0.00.7 PIN NO. 54 18 17-10 TYPE I I I/O NAME AND FUNCTION Ground: 0V reference. Power Supply: This is the power supply voltage for normal, idle, and power-down operation. Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 is also the multiplexed data and low-order address bus during accesses to external memory. External pull-ups are required during program verification. Port 0 can sink/source eight LS TTL inputs. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 receives the low-order address bytes during program memory verification. Port 1 can sink/source three LS TTL inputs, and drive CMOS inputs without external pull-ups. Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 emits the high-order address bytes during access to external memory and receives the high-order address bits and control signals during program verification. Port 2 can sink/source three LS TTL inputs, and drive CMOS inputs without external pull-ups. Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 can sink/source three LS TTL inputs, and drive CMOS inputs without external pull-ups. Port 3 also serves the special functions listed below: RxD (P3.0): Serial input port TxD (P3.1): Serial output port INT0 (P3.2): External interrupt INT1 (P3.3): External interrupt T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe Port 4: Port 4 is a 8-bit (LCC) bidirectional I/O port with internal pull-ups. Port 4 can sink/source three LS TTL inputs and drive CMOS inputs without external pull-ups. Port 5: Port 5 is a 8-bit (LCC) bidirectional I/O port with internal pull-ups. Port 5 can sink/source three LS TTL inputs and drive CMOS inputs without external pull-ups. Port 6: Port 6 is a specialized 8-bit bidirectional I/O port with internal pull-ups. This special port can sink/source three LS TTL inputs and drive CMOS inputs without external pull-ups. Port 6 can be used in a strobed or non-strobed mode of operation. Port 6 works in conjunction with four control pins that serve the functions listed below: ODS: Output data strobe IDS: Input data strobe BFLAG: Bidirectional I/O pin with internal pull-ups AFLAG: Bidirectional I/O pin with internal pull-ups Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal pull-down resistor permits a power-on reset using only an external capacitor connected to VCC. Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. ALE is activated at a constant rate of 1/6 the oscillator frequency except during an external data memory access, at which time one ALE is skipped. ALE can sink/source three LS TTL inputs and drive CMOS inputs without external pull-ups. This pin is also the program pulse during EPROM programming. Program Store Enable: The read strobe to external program memory. PSEN is activated twice each machine cycle during fetches from external program memory. However, when executing out of external program memory, two activations of PSEN are skipped during each access to external program memory. PSEN is not activated during fetches from internal program memory. PSEN can sink/source eight LS TTL inputs and drive CMOS inputs without an external pull-up. This pin should be tied low during programming. Instruction Execution Control/Programming Supply Voltage: When EA is held high, the CPU executes out of internal program memory, unless the program counter exceeds 0FFFH. When EA is held low, the CPU executes out of external program memory. EA must never be allowed to float. This pin also receives the 12.75V programming supply voltage (VPP) during EPROM programming. Crystal 1: Input to the inverting oscillator amplifier that forms the oscillator. This input receives the external oscillator when an external oscillator is used. Crystal 2: An output of the inverting amplifier that forms the oscillator. This pin should be floated when an external oscillator is used.
P1.0P1.7
27-34
I/O
P2.0P2.7
2-9
I/O
P3.0P3.7
36-43
I/O
36 37 38 39 40 41 42 43 P4.0P4.7 P5.0P5.7 P6.0P6.7 26-19 44-51 59-66
I O I I I I O O I/O I/O I/O
ODS IDS BFLAG AFLAG RST ALE/PROG
55 56 57 58 35 68
I I I/O I/O I I/O
PSEN
67
O
EA/VPP
1
I
XTAL1 XTAL2
53 52
I O
1996 Aug 16
3-295
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C451/83C451/87C451
I/O Port Structure
The 8XC451 has a total of seven parallel I/O ports. The first four ports, P0 through P3, are identical in function to those present on the 80C51 family. The added ports 4 and 5 are identical in function to port 1; that is, they are standard quasi-bidirectional ports with no alternate functions and the standard output drive characteristics. Port 6 is a specialized 8-bit bidirectional I/O port with internal pullups.
Processor Bus Interface
Port 6 allows the use of an 8XC451 as an element on a microprocessor type bus. The host processor could be a general purpose MPU or the data bus of a microcontroller like the 8XC451 itself. Setting up the 8XC451 as a processor bus interface allows single or multiple microcontrollers to be used on a bus as flexible peripheral processing elements. Applications can include: keyboard scanners, serial I/O controllers, servo controllers, etc. On reset, port 6 is programmed correctly (that is, Special Function registers CSR and P6) for use as a bus interface. This prevents the interface from disrupting data on the bus of a host processor during power-up.
Ports 4 and 5
Ports 4 and 5 are bidirectional I/O ports with internal pull-ups. Port 4 is an 8-bit port. Port 4 and port 5 pins with ones written to them, are pulled high by the internal pull-ups, and in that state can be used as inputs. Port 4 and 5 are addressed at the special function register addresses shown in Table 1.
Standard Quasi-bidirectional I/O Port
To use port 6 as a common I/O port, all of the control pins should be tied to ground. On hardware reset, bits 2-7 of the CSR are set to one. With the control pins grounded, the port's operation and electrical characteristics will be identical to port 1 on the 80C51. No further software initialization is required.
Port 6
Port 6 is a special 8-bit bidirectional I/O port with internal pull-ups (see Figure 1). This special port can sink/source three LS TTL inputs and drive CMOS inputs without external pullups. The flexibility of this port facilitates high-speed parallel data communications. This port can be used as a standard I/O port, or in strobed modes of operation in conjunction with four special control lines: ODS, IDS, AFLAG, and BFLAG. Port 6 operating modes are controlled by the port 6 control status register (CSR). Port 6 and the CSR are addressed at the special function register addresses shown in Table 1. The following four control pins are used in conjunction with port 6: ODS Output data strobe (Active Low) for port 6. ODS can be programmed to control the port 6 output drivers and the output buffer full flag (OBF), or to clear only the OBF flag bit in the CSR (output-always mode). ODS is active low for output driver control. the OBF flag can be programmed to be cleared on the negative or positive edge of ODS. IDS Input data strobe (Active Low) for port 6. IDS is used to control the port 6 input latch and input buffer full flag (IBF) bit in the CSR. The input data latch can be programmed to be transparent when IDS is low and latched on the positive transition of IDS, or to latch only on the positive transition of IDS. Correspondingly, the IBF flag is set on the negative or positive transition of IDS. BFLAG BFLAG is a bidirectional I/O pin which can be programmed to be an output, set high or low under program control, or to output the state of the input buffer full flag. BFLAG can also be programmed to input an enable signal for port 6. When BFLAG is used as an enable input, port 6 output drivers are in the high-impedance state, and the input latch does not respond to the IDS strobe when BFLAG is high. Both features are enabled when BFLAG is low. This feature facilitates the use of the SC8XC451 in bused multiprocessor systems. AFLAG AFLAG is a bidirectional I/O pin which can be programmed to be an output set high or low under program control, or to output the state of the output buffer full flag. AFLAG can also be programmed to be an input which selects whether the contents of the output buffer, or the contents of the port 6 control status register will output on port 6. This feature grants complete port 6 status to external devices. Port 6 can be used in a number of different ways to facilitate data communication. It can be used as a processor bus interface, as a standard quasi-bidirectional I/O port, or as a parallel printer port (either polled or interrupt driven).
Parallel Printer Port
The 8XC451 has the capacity to permit all of the intelligent features of a common printer to be handled by a single chip. The features of port 6 allow a parallel port to be designed with only line driving and receiving chips required as additional hardware. The onboard UART allows RS232 interfacing with only level shifting chips added. The 8-bit parallel ports 0 to 6 are ample to drive onboard control functions, even when ports are used for external memory access, interrupts, and other functions. The RAM addressing ability of ports 0 to 2 can be used to address up to 64k bytes of a hardware buffer/spooler. In addition, either end of a parallel interface can be implemented using port 6, and the interfaces can be interrupt driven or polled in either case. For more detailed information on port 6 usage, refer to the application notes entitled "80C451 Operation of Port 6" and "256k Centronics Printer Buffer Using the SC87C451 Microcontroller."
CONTROL STATUS REGISTER
The control status register (CSR) establishes the mode of operation for port 6 and indicates the current status of port 6 I/O registers. All control status register bits can be read and written by the CPU, except bits 0 and 1, which are read only. Reset writes ones to bits 2 through 7, and writes zeros to bits 0 and 1 (see Table 3). CSR.0 Input Buffer Full Flag (IBF) (Read Only) The IBF bit is set to a logic 1 when port 6 data is loaded into the input buffer under control of IDS. This can occur on the negative or positive edge of IDS, as determined by CSR.2 IBF is cleared when the CPU reads the input buffer register. CSR.1 Output Buffer Full Flag (OBF) (Read Only) The OBF flag is set to a logic 1 when the CPU writes to the port 6 output data buffer. OBF is cleared by the positive or negative edge of ODS, as determined by CSR.3. CSR.2 IDS Mode Select (IDSM) When CSR.2 = 0, a low-to-high transition on the IDS pin sets the IBF flag. The Port 6 input buffer is loaded on the IDS positive edge. When CSR.2 = 1, a high-to-low transition on the IDS pin sets the IBF flag. Port 6 input buffer is transparent when IDS is low, and latched when IDS is high.
1996 Aug 16
3-296
Others parts begin by 80
80-1 80-2 80-3
|
|
|
