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Part: 80C453X
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Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
80C453/83C453/87C453
DESCRIPTION
The Philips 8XC453 is an I/O expanded single-chip microcontroller fabricated with Philips high-density CMOS technology. Philips epitaxial substrate minimizes latch-up sensitivity. The 8XC453 is a functional extension of the 87C51 microcontroller with three additional I/O ports and four I/O control lines. The 8XC453 is available in 68-pin LCC packages. Four control lines associated with port 6 facilitate high-speed asynchronous I/O functions. The 87C453 includes an 8k × 8 EPROM, a 256 × 8 RAM, 56 I/O lines, two 16-bit timer/counters, a seven source, two priority level, nested interrupt structure, a serial I/O port for either a full duplex UART, I/O expansion, or multi-processor communications, and on-chip oscillator and clock circuits. The 87C453 has two software selectable modes of reduced activity for further power reduction; idle mode and power-down mode. Idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. Power-down mode freezes the oscillator, causing all other chip functions to be inoperative while maintaining the RAM contents.
LCC PIN FUNCTIONS
9 1 61
10
60
LCC
26
44
27 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Function EA/VPP P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC P4.7 P4.6 P4.5 P4.4 P4.3 Pin 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Function P4.2 P4.1 P4.0 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST P3.0/RxD P3.1/TxD P3.2/INTO P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD P5.0 P5.1 P5.2
43 Pin 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Function P5.3 P5.4 P5.5 P5.6 P5.7 XTAL2 XTAL1 V SS ODS IDS BFLAG AFLAG P6.0 P6.1 P6.2 P6.3 P6.4 P6.5 P6.6 P6.7 PSEN ALE/PROG
FEATURES
· 80C51 based architecture · Seven 8-bit I/O ports · Port 6 features:
Eight data pins Four control pins Direct MPU bus interface ISA Bus Interface Parallel printer interface IBF and OBF interrupts A flag latch on host write
SU00157
· On the microcontroller:
8k × 8 EPROM Quick pulse programming algorithm Two-level program security system 256 × 8 RAM Two 16-bit counter/timers Two external interrupts
· External memory addressing capability
64k ROM and 64k RAM
· Low power consumption:
Normal operation: less than 24mA at 5V, 16MHz Idle mode Power-down mode
· Reduced EMI · Full-duplex enhanced UART
Framing error detection Automatic address recognition
1996 Aug 15
3-311
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
80C453/83C453/87C453
ORDERING INFORMATION
EPROM1 P87C453EBAA P87C453EFAA P87C453EBLKA P87C453EFLKA OTP OTP UV UV ROMLESS P80C453EBAA P80C453EFAA ROM P83C453EBAA P83C453EFAA TEMPERATURE °C AND PACKAGE 68Pin Plastic Leaded Chip Carrier, 0 to +70 68Pin Plastic Leaded Chip Carrier, 40 to +85 68-Pin Ceramic Leaded Chip Carrier with window, 0 to +70 68-Pin Ceramic Leaded Chip Carrier with window, 40 to +85 FREQ. (MHz) 3.5 to 16 3.5 to 16 3.5 to 16 3.5 to 16 PKG. DWG # SOT188-3 SOT188-3 1473A 1473A
NOTE: 1. OTP = One-Time Programmable EPROM. UV = Erasable EPROM.
LOGIC SYMBOL
V CC XTAL1 PORT 0 ADDRESS AND DATA BUS VS S
XTAL2
SECONDARY FUNCTIONS
RST EA/VPP PSEN ALE/PROG RxD TxD INT0 INT1 T0 T1 WR RD
PORT 3
PORT 2
PORT 1
ADDRESS BUS
PORT 6 CONTROL
ODS IDS BFLAG AFLAG
PORT 6
PORT 5
PORT 4
SU00085
1996 Aug 15
3-312
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
80C453/83C453/87C453
BLOCK DIAGRAM
P0.0P0.7 P2.0P2.7 P4.0P4.7 P5.05.7
PORT 0 DRIVERS V CC VS S RAM ADDR REGISTER 256 BYTES RAM PORT 0 LATCH
PORT 2 DRIVERS
PORT 4 DRIVERS
PORT 5 DRIVERS
PORT 2 LATCH
PORT 4 LATCH
PORT 5 LATCH
8K x 8 EPROM
B REGISTER
ACC
STACK POINTER
TMP2
TMP1
PROGRAM ADDRESS REGISTER
BUFFER ALU PCON PSW TL1 PSW CSR SCON TMOD TH0 DPH SBUF TL0 DPL IE TCON TH1 AUXR IP PC INCREMENTER
INTERRUPT, SERIAL PORT AND TIMER BLOCKS
PROGRAM COUNTER PSEN ALE/PROG EAVPP RST PD TIMING AND CONTROL INSTRUCTION REGISTER
DPTR
PORT 1 LATCH
PORT 6 LATCH
PORT 3 LATCH
OSCILLATOR PORT 1 DRIVERS XTAL1 XTAL2 PORT 6 DRIVERS PORT 6 CONTROL/STATUS PORT 3 DRIVERS
P1.0P1.7
P6.0P6.7
IDS ODS BFLAG AFLAG
P3.0P3.7
SU00158
1996 Aug 15
3-313
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
80C453/83C453/87C453
PIN DESCRIPTION
MNEMONIC VSS VCC P0.00.7
PIN NO.
TYPE I I I/O
NAME AND FUNCTION Ground: 0V reference. Power Supply: This is the power supply voltage for normal, idle, and power-down operation. Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 is also the multiplexed data and low-order address bus during accesses to external memory. External pull-ups are required during program verification. Port 0 can sink/source eight LS TTL inputs. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 receives the low-order address bytes during program memory verification. Port 1 can sink/source three LS TTL inputs, and drive CMOS inputs without external pull-ups. Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 emits the high-order address bytes during access to external memory and receives the high-order address bits and control signals during program verification. Port 2 can sink/source three LS TTL inputs, and drive CMOS inputs without external pull-ups. Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 can sink/source three LS TTL inputs, and drive CMOS inputs without external pull-ups. Port 3 also serves the special functions listed below: RxD (P3.0): Serial input port TxD (P3.1): Serial output port INT0 (P3.2): External interrupt INT1 (P3.3): External interrupt T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe Port 4: Port 4 is an 8-bit bidirectional I/O port with internal pull-ups. Port 4 can sink/source three LS TTL inputs and drive CMOS inputs without external pull-ups. Port 5: Port 5 is an 8-bit bidirectional I/O port with internal pull-ups. Port 5 can sink/source three LS TTL inputs and drive CMOS inputs without external pull-ups. Port 6: Port 6 is a specialized 8-bit bidirectional I/O port with internal pull-ups. This special port can sink/source three LS TTL inputs and drive CMOS inputs without external pull-ups. Port 6 can be used in a strobed or non-strobed mode of operation. Port 6 works in conjunction with four control pins that serve the functions listed below: ODS: Output data strobe IDS: Input data strobe BFLAG: Bidirectional I/O pin with internal pull-ups AFLAG: Bidirectional I/O pin with internal pull-ups Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal pull-down resistor permits a power-on reset using only an external capacitor connected to VCC. Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. ALE is activated at a constant rate of 1/6 the oscillator frequency except during an external data memory access, at which time one ALE is skipped. ALE can sink/source three LS TTL inputs and drive CMOS inputs without external pull-ups. This pin is also the program pulse during EPROM programming. Program Store Enable: The read strobe to external program memory. PSEN is activated twice each machine cycle during fetches from external program memory. However, when executing out of external program memory, two activations of PSEN are skipped during each access to external program memory. PSEN is not activated during fetches from internal program memory. PSEN can sink/source eight LS TTL inputs and drive CMOS inputs without an external pull-up. This pin should be tied low during programming. Instruction Execution Control/Programming Supply Voltage: When EA is held high, the CPU executes out of internal program memory, unless the program counter exceeds 1FFFH. When EA is held low, the CPU executes out of external program memory. EA must never be allowed to float. This pin also receives the 12.75V programming supply voltage (VPP) during EPROM programming. Crystal 1: Input to the inverting oscillator amplifier that forms the oscillator. This input receives the external oscillator when an external oscillator is used. Crystal 2: An output of the inverting amplifier that forms the oscillator. This pin should be floated when an external oscillator is used.
54 18 17-10
P1.0P1.7
27-34
I/O
P2.0P2.7
2-9
I/O
P3.0P3.7
36-43
I/O
36 37 38 39 40 41 42 43 P4.0P4.3 P4.0P4.7 P5.0P5.7 P6.0P6.7 26-19 44-51 59-66
I O I I I I O O I/O I/O I/O I/O
ODS IDS BFLAG AFLAG RST ALE/PROG
55 56 57 58 35 68
I I I/O I/O I I/O
PSEN
67
O
EA/VPP
1
I
XTAL1 XTAL2
53 52
I O
1996 Aug 15
3-314
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
80C453/83C453/87C453
Table 1.
SYMBOL ACC* B*
87C453 Special Function Registers
DESCRIPTION Accumulator B register DIRECT ADDRESS E0H F0H BIT NAMES AND ADDRESSES MSB E7 F7 EF E6 F6 EE MB0 E5 F5 ED MA1 E4 F4 EC MA0 E3 F3 EB OBFC E2 F2 EA IDSM E1 F1 E9 OBF LSB E0 F0 E8 IBF FCH RESET VALUE 00H 00H
CSR*# DPTR DPH DPL
Port 6 command/status Data pointer (2 bytes) Data pointer high Data pointer low
E8H
MB1
83H 82H BF BE POB BD PIB BC PS BB PT1 BA PX1 B9 PT0 B8 PX0
00H 00H
IP*
Interrupt priority
B8H
x0000000B
AUXR#
Auxiliary register
8EH
AF
AE IOB B6 96 A6 B6 C6 CE DE SMOD0 D6 AC
AD IIB 85 95 A5 B5 C5 CD DD D5 F0
AC ES 84 94 A4 B4 C4 CC DC POF1 D4 RS1
AB ET1 83 93 A3 B3 C3 CB DB GF1 D3 RS0
AA EX1 82 92 A2 B2 C2 CA DA GF0 D2 OV
AF A9 ET0 81 91 A1 B1 C1 C9 D9 PD D1
AO A8 EX0 80 90 A0 B0 C0 C8 D8 IDL D0 P
x0000000B
IE* P0* P1* P2* P3* P4*# P5*# P6*# PCON
Interrupt enable Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Power control
A8H 80H 90H A0H B0H C0H C8H D8H 87H
EA 87 97 A7 B7 C7 CF DF SMOD1 D7
00000000B FFH FFH FFH FFH FFH FFH FFH 00xx0000B
PSW* SADDR# SADEN# SBUF
Program status word Slave Address Slave Address Mask Serial data buffer
D0H A9H B9H 99H
CY
00H 00H 00H xxxxxxxxB
9F SCON* SP Serial port control Stack pointer 98H 81H 8F TCON* TMOD TH0 TH1 TL0 TL1 Timer/counter control Timer/counter mode Timer 0 high byte Timer 1 high byte Timer 0 low byte Timer 1 low byte 88H 89H 8CH 8DH 8AH 8BH TF1 GATE SM0
9E SM1
9D SM2
9C REN
9B TB8
9A RB8
99 TI
98 RI 00H 07H
8E TR1 C/T
8D TF0 M1
8C TR0 M0
8B IE1 GATE
8A IT1 C/T
89 IE0 M1
88 IT0 M0 00H 00H 00H 00H 00H 00H
NOTES: * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. 1. REset value depends on reset source.
1996 Aug 15
3-315
Others parts begin by 80
80-1 80-2 80-3
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