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Details, datasheet, quote on part number: 8XC562
 
 
Part number8XC562
Category
Description
CompanyN.A.
DatasheetDownload 8XC562 datasheet
 


 
Specifications, Features, Applications

The is a stand-alone high-performance microcontroller designed for use in real-time applications such as instrumentation, industrial control, and automotive control applications such as engine management and transmission control. The device provides, in addition to the 80C51 standard functions, a number of dedicated hardware functions for these applications. The 8XC552 single-chip 8-bit microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The 8XC552 uses the powerful instruction set of the 80C51. Additional special function registers are incorporated to control the on-chip peripherals. Three versions of the derivative exist although the generic term "8XC552" is used to refer to family members: 83C552: 8k bytes mask-programmable ROM, 256 bytes RAM 87C552: 8k bytes EPROM, 256 bytes RAM 80C552: ROMless version of the 83C552 The 8XC552 contains a nonvolatile 8 read-only program memory, a volatile 8 read/write data memory, five 8-bit I/O ports and one 8-bit input port, two 16-bit timer/event counters (identical to the timers of the 80C51), an additional 16-bit timer coupled to capture and compare latches, a fifteen-source, two-priority-level, nested interrupt structure, an 8-input ADC, a dual DAC pulse width modulated interface, two serial interfaces (UART and I2C bus), a "watchdog" timer, and on-chip oscillator and timing circuits. For systems that require extra capability, the 8XC552 can be expanded using standard TTL compatible memories and logic The 8XC552 has two software selectable modes of reduced activity for further power reduction--Idle and Power-down. The idle mode freezes the CPU and resets Timer T2 and the ADC and PWM circuitry but allows the other timers, RAM, serial ports, and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to become inoperative.

flag locations are undefined after RESET. The interrupt vector for SIO1 is not used.
Port lines P1.6 and P1.7 are not open drain but have the same

standard configuration and electrical characteristics as P1.0-P1.5. Port lines P1.6 and P1.7 have alternative functions.

consequently the two high-order bits 6 and 7 of SFR ADCON are not implemented. These two locations are undefined after RESET. The 8-bit result of an A/D conversion is present in SFR ADCH. The result can always be calculated from the formula: * AV ref* AV ref) * AV ref*

The A/D conversion time is 24 machine cycles instead of 50 machine cycles, and the sampling time is 6 machine cycles instead of 8 machine cycles. The conversion time takes 3 machine cycles per bit.

renamed to SIO, SBUF, and SCON. The interrupt related flags ES0 and PS0 are renamed ES and PS. Interrupt source S0 is renamed S. The serial I/O function remains the same.

Program Memory The 8XC552 contains 8k bytes of on-chip program memory which can be extended to 64k bytes with external memories (see Figure 1). When the EA pin is held high, the 8XC552 fetches instructions from internal ROM unless the address exceeds 1FFFH. Locations 2000H to FFFFH are fetched from external program memory. When the EA pin is held low, all instruction fetches are from external memory. ROM locations to 0073H are used by interrupt service routines. Data Memory The internal data memory is divided into 3 sections: the lower 128 bytes of RAM, the upper 128 bytes of RAM, and the 128-byte special function register areas. The lower 128 bytes of RAM are directly and indirectly addressable. While RAM locations to 255 and the special function register area share the same address space, they are accessed through different addressing modes. RAM locations to 255 are only indirectly addressable, and the special function registers are only directly addressable. All other aspects of the internal RAM are identical to the 8051. The stack may be located anywhere in the internal RAM by loading the 8-bit stack pointer. Stack depth is 256 bytes maximum. Special Function Registers The special function registers (directly addressable only) contain all of the 8XC552 registers except the program counter and the four register banks. Most of the 56 special function registers are used to control the on-chip peripheral hardware. Other registers include arithmetic registers (ACC, B, PSW), stack pointer (SP), and data pointer registers (DHP, DPL). Sixteen of the SFRs contain 128 directly addressable bit locations. Table 1 lists the 8XC552's special function registers. The standard 80C51 SFRs are present and function identically in the 8XC552 except where noted in the following sections.

The 83C562 has been derived from the 8XC552 with the following changes:

The SIO1 (I2C) interface has been omitted. The output of port lines P1.6 and P1.7 have a standard

The resolution of the A/D converter is decreased from 10 bits to 8 The time of an A/D conversion has decreased from 50 machine

cycles to 24 machine cycles. All other functions, pinning and packaging are unchanged. This chapter of the users' guide can be used for the 83C562 by omitting or changing the following:

are not implemented. The two SIO1 related flags ES1 in SFR IEN0 and PS1 in SFR IP0 are also not implemented. These two

(FFH) 255 SPECIAL FUNCTION REGISTERS INTERNAL (EA = 1) EXTERNAL (EA (7FH) 127 INTERNAL DATA RAM

Figure 1. Memory Map Timer T2 Timer a 16-bit timer consisting of two registers TMH2 (HIGH byte) and TML2 (LOW byte). The 16-bit timer/counter can be switched off or clocked via a prescaler from one of two sources: or an external signal. When Timer T2 is configured as a counter, the prescaler is clocked by an external signal (P1.4). A rising edge on T2 increments the prescaler, and the maximum repetition rate is one count per machine cycle (1MHz with a 12MHz oscillator). The maximum repetition rate for Timer T2 is twice the maximum repetition rate for Timer 0 and Timer (P1.4) is sampled at S2P1 and again at S5P1 (i.e., twice per machine cycle). A rising edge is detected when T2 is LOW during one sample and HIGH during the next sample. To ensure that a rising edge is detected, the input signal must be LOW for at least 1/2 cycle and then HIGH for at least 1/2 cycle. If a rising edge is detected before the end of S2P1, the timer will be incremented during the following cycle; otherwise it will be incremented one cycle later. The prescaler has a programmable division factor or 8 and is cleared if its division factor or input source is changed, or if the timer/counter is reset. Timer T2 may be read "on the fly" but possesses no extra read latches, and software precautions may have to be taken to avoid misinterpretation in the event of an overflow from least to most significant byte while Timer T2 is being read. Timer T2 is not loadable and is reset by the RST signal by a rising edge on the input signal RT2, if enabled. RT2 is enabled by setting bit T2ER (TM2CON.5). When the least significant byte of the timer overflows or when a 16-bit overflow occurs, an interrupt request may be generated. Either or both of these overflows can be programmed to request an interrupt. In both cases, the interrupt vector will be the same. When the lower byte (TML2) overflows, flag (TM2CON) is set and flag (TM2IR) is set when TMH2 overflows. These flags are set one cycle after an overflow occurs. Note that when T20V is set, T2B0 will also be set. To enable the byte overflow interrupt, bits ET2 (IEN1.7, enable overflow interrupt, see Figure 2) and T2IS0 (TM2CON.6, byte overflow interrupt select) must be set. Bit (TM2CON.4) is the Timer T2 byte overflow flag. To enable the 16-bit overflow interrupt, bits ET2 (IE1.7, enable overflow interrupt) and (TM2CON.7, 16-bit overflow interrupt select) must be set. Bit (TM2IR.7) is the Timer T2 16-bit overflow flag. All interrupt flags must be reset by software. To enable both byte and 16-bit overflow, T2IS0 and T2IS1 must be set and two interrupt service routines are required. A test on the overflow flags indicates which routine must be executed. For each routine, only the corresponding overflow flag must be cleared. Timer T2 may be reset by a rising edge (P1.5) if the Timer T2 external reset enable bit T2CON is set. This reset also clears the prescaler. In the idle mode, the timer/counter and prescaler are reset and halted. Timer T2 is controlled by the TM2CON special function register (see Figure 3).

SYMBOL ACC* ADCH# ADCON# B* CTCON# CML1# CML0# DPTR: DPH DPL

DESCRIPTION Accumulator A/D converter high Adc control B register Capture control Capture high 3 Capture high 2 Capture high 1 Capture high 0 Compare high 2 Compare high 1 Compare high 0 Capture low 3 Capture low 2 Capture low 1 Capture low 0 Compare low 2 Compare low 1 Compare low 0 Data pointer (2 bytes) Data pointer high Data pointer low DIRECT ADDRESS C5H F0H EBH CFH CEH CDH CCH CBH CAH C9H AFH AEH ADH ACH ABH AAH F6 CTP3 ADEX F5 CTN2 ADCI F4 CTP2 ADCS F0 CTP0 BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB LSB E1 E0 RESET VALUE 00H xxxxxxxxB xx000000B 00H xxxxxxxxB 00H xxxxxxxxB 00H


PSW* Program status word CY * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs.




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