Details, datasheet, quote on part number: AD640N
DatasheetDownload AD640N datasheet


Features, Applications

FEATURES Complete, Fully Calibrated Monolithic System Five Stages, Each Having 10 dB Gain, 350 MHz BW Direct Coupled Fully Differential Signal Path Logarithmic Slope, Intercept and AC Response are Stable Over Full Military Temperature Range Dual Polarity Current Outputs Scaled 1 mA/Decade Voltage Slope Options (1 V/Decade, 100 mV/dB, etc.) Low Power Operation (Typically 5 V) Low Cost Plastic Packages Also Available APPLICATIONS Radar, Sonar, Ultrasonic and Audio Systems Precision Instrumentation from to 120 MHz Power Measurement with Absolute Calibration Wide Range High Accuracy Signal Compression Alternative to Discrete and Hybrid IF Strips Replaces Several Discrete Log Amp ICs PRODUCT DESCRIPTION

with an intercept (logarithmic offset) 1 mV dc. An integral X10 attenuator provides an alternative input range 2 V dc. Scaling is also guaranteed for sinusoidal inputs. The AD640B is specified for the industrial temperature range to +85C and the AD640T, available processed to MILSTD-883B, for the military range to +125C. Both are available in 20-pin side brazed ceramic DIPs or leadless chip carriers (LCC). The AD640J is specified for the commercial temperature range to +70C, and is available in both 20-pin plastic DIP (N) and PLCC (P) packages. This device is now available to Standard Military Drawing (DESC) number 5962-9095501MRA and 5962-9095501M2A.

The is a complete monolithic logarithmic amplifier. A single AD640 provides dB of dynamic range for frequencies from to 120 MHz. Two AD640s in cascade can provide dB of dynamic range at reduced bandwidth. The AD640 uses a successive detection scheme to provide an output current proportional to the logarithm of the input voltage. It is laser calibrated to close tolerances and maintains high accuracy over the full military temperature range using supply voltages from 7.5 V. The AD640 comprises five cascaded dc coupled amplifier/limiter stages, each having a small signal voltage gain 10 dB and 3 dB bandwidth of 350 MHz. Each stage has an associated full-wave detector, whose output current depends on the absolute value of its input voltage. The five outputs are summed to provide the video output (when low-pass filtered) scaled 1 mA per decade (50 A per dB). On chip resistors can be used to convert this output current to a voltage with several convenient slope options. A balanced signal output +50 dB (referred to input) is provided to operate AD640s in cascade. The logarithmic response is absolutely calibrated to within l dB for dc or square wave inputs from 200 mV,

1. Absolute calibration of a wideband logarithmic amplifier is unique. The is a high accuracy measurement device, not simply a logarithmic building block. 2. Advanced design results in unprecedented stability over the full military temperature range. 3. The fully differential signal path greatly reduces the risk of instability due to inadequate power supply decoupling and shared ground connections, a serious problem with commonly used unbalanced designs. 4. Differential interfaces also ensure that the appropriate ground connection can be chosen for each signal port. They further increase versatility and simplify applications. The signal input impedance k in shunt with ~2 pF. 5. The dc coupled signal path eliminates the need for numerous interstage coupling capacitors and simplifies logarithmic conversion of subsonic signals. 6. The low input offset voltage (200 V max) ensures good accuracy for low level dc inputs. 7. Thermal recovery "tails," which can obscure the response when a small signal immediately follows a high level input, have been minimized by special attention to design details. 8. The noise spectral density of 2 nV/Hz results in a noise floor ~23 V rms (80 dBm) at a bandwidth of 100 MHz. The dynamic range using cascaded AD640s can be extended dB by the inclusion of a simple filter between the two devices.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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Model Transfer Function 1 Parameter SIGNAL INPUTS (Pins 1, 20) Input Resistance Input Offset Voltage vs. Temperature Over Temperature vs. Supply Input Bias Current Input Bias Offset Common-Mode Range INPUT ATTENUATOR (Pins and 19) Attenuation 2 Input Resistance SIGNAL OUTPUT (Pins 10, 11) Small Signal Gain 4 Peak Differential Output 5 Output Resistance Quiescent Output Voltage LOGARITHMIC OUTPUT 6 (Pin 14) Voltage Compliance Range Slope Current, I Y Accuracy vs. Temperature Accuracy vs. Supply Intercept Voltage 7, VX vs. Temperature Over Temperature vs. Supply Logarithmic Offset (Alt. Definition V X) vs. Temperature Over Temperature vs. Supply Intercept Voltage Using Attenuator Zero Signal Output Current 3 ITC Disabled Maximum Output Current APPLICATIONS RESISTORS (Pins 17) DC LINEARITY VIN 100 mV TOTAL ABSOLUTE DC ACCURACY VIN 100 mV8 Over Temperature Over Supply Range VIN 200 mV Using Attenuator VIN 1 V Over Temperature VIN 2 V POWER REQUIREMENTS Voltage Supply Range Quiescent Current 9 +VS (Pin 12) VS (Pin 7)

0.3 0.95 TMIN to TMAX +VS V 0.85 TMIN to TMAX V 61.5 TMIN to TMAX V 8.25 Pin 8 to COM

Model Parameter SIGNAL INPUTS (Pins 1, 20) Input Capacitance Noise Spectral Density Tangential Sensitivity 3 dB BANDWIDTH Each Stage All Five Stages LOGARITHMIC OUTPUTS 6 Slope Current, = 1 MHz = 30 MHz = 60 MHz = 90 MHz = 120 MHz Intercept, Dual = 1 MHz = 30 MHz = 60 MHz = 90 MHz = 120 MHz AC LINEARITY 40 dBm to 2 dBm 12 35 dBm to 10 dBm 12 75 dBm to 0 dBm 10 70 dBm to 10 dBm 10 75 dBm to +15 dBm 13 PACKAGE OPTION 20-Pin Ceramic DIP Package (D) 20-Pin Leadless Ceramic Chip Carrier (E) 20-Pin Plastic DIP Package (N) 20-Pin Plastic Leadless Chip Carrier (P) NUMBER OF TRANSISTORS

NOTES 1 Logarithms to base 10 are used throughout. The response is independent of the sign of V IN. 2 Attenuation ratio trimmed to calibrate intercept 10 mV when in use. It has a temperature coefficient of +0.30%/ C. 3 The zero-signal current is a function of temperature unless internal temperature compensation (ITC) pin is grounded. 4 Overall gain is trimmed using 200 V square wave at 2 kHz, corrected for the onset of compression. 5 The fully limited signal output will appear be a square wave; its amplitude is proportional to absolute temperature. 6 Currents defined as flowing into Pin 14. See FUNDAMENTALS OF LOGARITHMIC CONVERSION for full explanation of scaling concepts. Slope is measured by linear regression over central region of transfer function. 7 The logarithmic intercept in dBV (decibels relative V) is defined as 20 LOG 10 (VX/1 V). 8 Operating in circuit of Figure 24 using 0.1% accurate values for R LA and RLB. Includes slope and nonlinearity errors. Input offset errors also included for VIN >3 mV dc, and over the full input range in ac applications. 9 Essentially independent of supply voltages. 10 Using the circuit of Figure 27, using cascaded AD640s and offset nulling. Input is sinusoidal, 0 dBm 223 mV rms. 11 For a sinusoidal signal (see EFFECT OF WAVEFORM ON INTERCEPT). Pin 8 on second AD640 must be grounded to ensure temperature stability of intercept for dual AD640 system. 12 Using the circuit of Figure 24, using single AD640 and offset nulling. Input is sinusoidal, 0 dBm 223 mV rms. 13 Using the circuit of Figure 32, using cascaded AD640s and attenuator. Square wave input. All min and max specifications are guaranteed, but only those in boldface are 100% tested on all production units. Results from those tests are used to calculate outgoing quality levels. Specifications subject to change without notice.

JC (C/W) 20-Pin Ceramic DIP Package (D-20) 20-Pin Leadless Ceramic Chip Carrier (E-20A) 20-Pin Plastic DIP Package (N-20) 20-Pin Plastic Leadless Chip Carrier (P-20A)


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