|Datasheet||Download AK93C45A datasheet
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1 ADVANCED CMOS 1%PROM TECHNOLOGY READ/WRITE NON-VOLATILE MEMORY WIDE VCC OPERATION VCC 5.5V 1024 bits, X 16 organization SERIAL INTERFACE - Interfaces with popular microcontrollers and standard microprocessors LOW POWER CONSUMPTION - 0,5mA max. Read Operation u A Max. Standby Automatic address increment (READ) Automatic write cycle time-out with auto-ERASE Busy/Ready status signal Software controlled write protection IDEAL FOR LOW DENSITY DATA STORAGE - Low cost, space saving, 8-pin packageDATA FUWAMPS AND AUTO ERASE > +1024bit ADD. BUFFERS DECODER
The a 1024-bit serial CMOS EZPROM divided into 64 registers of 16 bits each. The AK93C45A has 4 instructions such as READ, WRITE, EWEN and EWDS. Those instructions control the AK93C45A. The AK93C45A can operate full function under wide operating voltage range from to 5.5V. The charge up circuit is integrated for high voltage generation that is used for write operation. A serial interface of AK93C45A, consisting of chip select (CS), serial clock (SK), data-in (Dl) and data-out (DO), can easily be controlled by popular microcontrollers or standard microprocessors. AK93C45A takes in the write data from data input pin (Dl) to a register synchronously with rising edge of input pulse of serial clock pin (SK). And at read operation, AK93C45A takes out the read data from a register to data output pin (DO) synchronously with rising edge of SK. The DO pin is usually in high impedance state. The DO pin outputs "L" or "H" in case of data output or Busy/Ready signal output.
o Software controlled write protection When Vcc is applied to the pafl, the part automatically powers up in the ERASEANRITE Disable state. In the ERASE/WRITE disable state, execution of WRITE instruction is disabled. Before WRITE instruction is executed, EWEN instruction must be executed. The ERASEAMRITE enable state continues until EWDS instruction is executed or Vcc is removed from the part. Execution of a read instruction is independent of both EWEN and EWDS instructions.
o Busy/Ready status signal After a write instruction, the DO output serves as a Busy/Ready status indicator. After the falling edge of the CS initiates the self-timed programming cycle, the DO indicates the Busy/Ready status of the chip if the CS is brought high after a minimum of 250ns (Tcs). DO=logical "O" indicates that programming is still in progress. DO=logicaI "1" indicates that the register at the address specified in the instruction has been written with the new data pattern contained in the instruction and the part is ready for a next instruction. The Busy/Ready status indicator is only valid when CS is active (high). When CS is low, the DO output goes into a high impedance state. The Busy/Ready signal outputs until a start bit (Logic"l") of the next instruction is given to the part.
of Products Memory size 1024 bits 1024 bits 1024 bits Temp. Range -40~x85~ -40~ti85~ Vcc - 5.5V Package 8pin Plastic DIP 8pin Plastic SOP 8pin Plastic TSSOP
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