|Description||Ic-512k Flash Memory|
|Datasheet||Download AM28F512150PC datasheet
512 Kilobit x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory
s High performance 70 ns maximum access time s CMOS Low power consumption 30 mA maximum active current 100 µA maximum standby current No data retention power consumption s Compatible with JEDEC-standard byte-wide 32-Pin EPROM pinouts 32-pin PDIP 32-pin PLCC 32-pin TSOP s 10,000 write/erase cycles minimum s Write and erase voltage ±5% s Latch-up protected 100 mA from V to VCC V s Flasherase Electrical Bulk Chip-Erase One second typical chip-erase s Flashrite Programming 10 µs typical byte-program One second typical chip program s Command register architecture for microprocessor/microcontroller compatible write interface s On-chip address and data latches s Advanced CMOS flash memory technology Low cost single transistor memory cell s Automatic write/erase pulse stop timer
The 512 K bit Flash memory organized as 64 Kbytes of 8 bits each. AMD's Flash memories offer the most cost-effective and reliable read/ write non-volatile random access memor y. The Am28F512 is packaged in 32-pin PDIP, PLCC, and TSOP versions. It is designed to be reprogrammed and erased in-system or in standard EPROM programmers. The Am28F512 is erased when shipped from the factory. The standard Am28F512 offers access times as fast as 70 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the Am28F512 has separate chip enable (CE#) and output enable (OE#) controls. AMD's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The Am28F512 uses a command register to manage this functionality, while maintaining a standard JEDEC Flash Standard 32-pin pinout. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming. AMD's Flash technology reliably stores memory contents even after 10,000 erase and program cycles. The AMD cell is designed to optimize the erase and proPublication# 11561 Rev: G Amendment/+2 Issue Date: January 1998
gramming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The Am28F512 uses V PP high voltage input to perform the Flasherase and Flashrite algorithms. The highest degree of latch-up protection is achieved with AMD's proprietary non-epi process. Latch-up protection is provided for stresses mA on address and data pins from V to VCC +1 V. The Am28F512 is byte programmable using 10 ms programming pulses in accordance with AMD's Flashrite programming algorithm. The typical room temperature programming time of the Am28F512 is one second. The entire chip is bulk erased using 10 ms erase pulses according to AMD's Flasherase algorithm. Typical erasure at room temperature is accomplished in less than one second. The windowed package and the 15-20 minutes required for EPROM erasure using ultra-violet light are eliminated. Commands are written to the command register using standard microprocessor write timings. Register contents serve as inputs to an internal state-machine which controls the erase and programming circuitry. During
write cycles, the command register internally latches address and data needed for the programming and erase operations. For system design simplification, the Am28F512 is designed to support either WE# or CE# controlled writes. During a system write cycle, addresses are latched on the falling edge of WE# or CE# whichever occurs last. Data is latched on the rising edge of WE# or CE# whichever occurs first. To simplify the following discussion, the WE# pin is used as the write cycle control pin throughout the rest of this text. All setup and hold times are with respect to the WE# signal.
AMD's Flash technology combines years of EPROM and EEPROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The Am28F512 electrically erases all bits simultaneously using Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection.
DQ0DQ7 VCC VSS VPP Erase Voltage Switch State Control Command Register To Array Input/Output BuffersLow VCC Detector Program/Erase Pulse Timer A0A15 Address Latch
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