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Part: AM29F010-120PC
Category:
Description: Ic-1mb 5v Flash Memory
Company:
Datasheet: Download AM29F010-120PC datasheet File size : 1483 kB
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FINAL
Am29F010
1 Megabit (131,072 x 8-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory
DISTINCTIVE CHARACTERISTICS
s 5.0 V ± 10% for read and write operations -- Minimizes system level power requirements s Compatible with JEDEC-standards -- Pinout and software compatible with single-power-supply Flash -- Superior inadvertent write protection s 32-pin PLCC 32-pin TSOP 32-pin PDIP s Minimum 100,000 write/erase cycles guaranteed s High performance -- 45 ns maximum access time s Sector erase architecture -- Uniform sectors of 16 Kbytes each -- Any combination of sectors can be erased. Also supports full chip erase s Sector protection -- Hardware method that disables any combination of sector(s) from write or erase operations s Embedded EraseTM Algorithms -- Automatically preprograms and erases the chip or any sector s Embedded ProgramTM Algorithms -- Automatically programs and verifies data at specified address s Data Polling and Toggle Bit feature for detection of program or erase cycle completion s Low power consumption -- 30 mA maximum active read current -- 50 mA maximum program/erase current s Enhanced power management for standby mode -- <25 µA typical standby current
5.0 V-only Flash
GENERAL DESCRIPTION
The Am29F010 is a 1 Mbit, 5.0 Volt-only Flash memory organized as 128 Kbytes of 8 bits each. The 1 Mbit of data is divided into 8 sectors of 16 Kbytes for flexible erase capability. The 8 bits of data will appear on DQ0 DQ7. The Am29F010 is offered in 32-pin packages which allows for upgrades to 4 Mbit densities in the s a m e pin out. This device is designed to be programmed in-system with the standard system 5.0 Volt VCC supply. 12.0 Volt VPP is not required for program or e ra s e operations. The device can also be reprogrammed in standard EPROM programmers. The standard Am29F010 offers access times between 45 ns and 120 ns allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls. The Am29F010 is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 12.0 Volt Flash or EPROM devices. The Am29F010 is programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. This device also features a sector erase architecture. This allows for sectors of memory to be erased and reprogrammed without affecting the data contents of
Publication# 16736 Rev: F Amendment/+1 Issue Date: April 1997
other sectors. A sector is typically erased and verified within one second. The Am29F010 is erased when shipped from the factory. The Am29F010 device also features hardware sector protection. This feature will disable both program and erase operations in any combination of eight sectors of memory. The device features single 5.0 Volt power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector aut o m a t i c a l l y inhibits write operations during power transitions. The end of program or erase is detected by the Data Polling of DQ7 or by the Toggle Bit (DQ6). Once the end of a program or erase cycle has been completed, the device automatically resets to the read mode. A M D 's F l a s h t e c h n o l o g y c o m b i n e s ye a r s o f Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The Am29F010 memory electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The bytes are programmed one byte at a time
using the EPROM programming mechanism of hot electron injection.
Flexible Sector-Erase Architecture
s Eight 16 Kbyte sectors s Individual-sector or multiple-sector erase capability s Sector protection is user definable
SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0
16 Kbyte 16 Kbyte 16 Kbyte 16 Kbyte 16 Kbyte 16 Kbyte 16 Kbyte 16 Kbyte
1FFFFh 1BFFFh 17FFFh 13FFFh 0FFFFh 0BFFFh 07FFFh 03FFFh 00000h
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2
Am29F010
PRODUCT SELECTOR GUIDE
Family Part No: Ordering Part No: VCC = 5.0 V ± 5% VCC = 5.0 V ± 10% Max Access Time (ns) CE (E) Access (ns) OE (G) Access (ns) 45 45 25 -45 -55 (P) -55 (J,E,F) 55 55 30 -70 70 70 30 -90 90 90 35 -120 120 120 50 Am29F010
BLOCK DIAGRAM
5.0 V-only Flash
DQ0DQ7 VCC VSS
Erase Voltage Switch
Input/Output Buffers
WE
State Control Command Register PGM Voltage Switch Chip Enable Output Enable Logic Data Latch
CE OE
Embedded Algorithms VCC Detector Timer Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0A16
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Am29F010
3
CONNECTION DIAGRAMS PDIP
A1 2 A1 5
NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE (W) NC A14 A13 A8 A9 A11 OE (G) A10 CE (E) DQ7 DQ6 DQ5 DQ4 DQ3
PLCC
WE (W) A1 6 VCC NC NC
43 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13
2
1 32 31 30 29 28 27 26 25 24 23 22 21 A14 A13 A8 A9 A11 OE (G) A10 CE (E) DQ7
14 15 16 17 18 19 20
VSS DQ3
DQ4
DQ5
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DQ1 DQ2
DQ6
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TSOP
A11 A9 A8 A13 A14 NC WE VCC NC A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
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29F010 Standard Pinout
OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A11 A9 A8 A13 A14 NC WE VCC NC A16 A15 A12 A7 A6 A5 A4
29F010 Reverse Pinout
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4
Am29F010
PIN CONFIGURATION
A0A16 CE DQ0DQ7 NC OE VCC = 17 Addresses = Chip Enable = 8 Data Inputs/Outputs = Pin Not Connected Internally = Output Enable = +5.0 Volt Single-Power Supply (±10% for -55, -70, -90, -120) or (±5% for -45) = Device Ground
LOGIC SYMBOL
17 A0A16 DQ0DQ7 CE (E) OE (G) WE (W) 8
VSS WE
5.0 V-only Flash
= Write Enable
16736F-7
Am29F010
5
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