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Part: AN1891
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RF COMMUNICATIONS PRODUCTS
AN1891 SA8025 Fractional-N synthesizer for 2GHz band applications
Wing S. Djen 1997 Aug 20
Philips Semiconductors
Philips Semiconductors
Application note
SA8025 Fractional-N synthesizer for 2GHz band applications
Author: Wing S. Djen
INTRODUCTION
The SA8025 is a 3V, 1.8GHz, SSOP 20-pin packaged fractional-N phase locked-loop (PLL) frequency synthesizer. It is targeted for systems like the Japan Personal Handy Phone System (PHS, formerly PHP) which demands fast switching time and good noise performance. Built on the QUBiC BiCMOS process, it has phase detectors with maximum frequency of 5MHz and an auxiliary synthesizer that can operate up to 150MHz. This design was based on the UMA1005 (all CMOS), an earlier version fractional-N synthesizer which requires an external prescaler for 1 and 2GHz applications. There is also a 1GHz version fractional-N PLL frequency synthesizer, the SA7025, available for systems operating under 1GHz. One should expect the performance of the SA8025 and SA7025 to be comparable to the UMA1005 with an extra prescaler. This application note will serve as a supplement to the application note for the UMA1005 (Report No: SCO/AN92002) or as a stand-alone document specifically for the SA8025.
AN1891
The advantage of fractional-N synthesizers is two-fold. Since the close-in noise floor is directly related to total divide ratio (N), reducing N five or eight times theoretically implies a close-in noise floor improvement of 14dB (20log(5)) or 18dB (20log(8)), respectively. At the same time, the comparison breakthrough will be 5 or 8 times further away than it would be if a conventional synthesizer were used. This allows a wider loop filter to be used, thus achieving a faster switching time. Faster switching is also achieved due to the higher number of comparison cycles. To synthesize 1680, 1680.3, 1680.6MHz with channel spacing = 300kHz
Conventional syn. fVCO = fCOMP (N) 1680 = 0.3 (5600) 1680.3 = 0.3 (5601) 1680.6 = 0.3 (5602) fCOMP = fC H = 0.3MHz SA8025 (mod 5) fVCO = fCOMP (N + NF/5) 1680 = 1.5 (1120 + 0/5) 1680.3 = 1.5 (1120 + 1/5) 1680.6 = 1.5 (1120 + 2/5) fCOMP = 5 x fCH = 1.5MHz SA8025 (mod 8) fVCO = fCOMP (N + NF/8) 1680 = 2.4 (700 + 0/8) 1680.3 = 2.4 (700 + 1/8) 1680.6 = 2.4 (700 + 2/8) fCOMP = 8 x fCH = 2.4MHz
OVERVIEW OF THE FRACTIONAL-N FREQUENCY SYNTHESIZER
Figure 1 shows the basic building blocks of a PLL frequency synthesizer. It consists of a programmable reference divider, phase detector and programmable RF divider (prescaler and main divider). The low-pass filter and voltage-controlled oscillator (VCO) are external to provide design flexibility. The loop has a self-correction mechanism which forces comparison frequency fCOMP = fCOMP'. Since fCOMP = fREF/M and fCOMP' = fVCO/N, the desired frequency becomes fVCO = (fREF/M)N. M (reference divider) is fixed for generating fCOMP. By incrementing or decrementing the value of N, different frequencies can be synthesized.
Phase Referenece Detector Divider fCOMP ÷M fCOMP' Prescaler and Conventional Fractional-N Main Synth Synth Divider NF ) ÷ (N ) ÷N Q Low-Pass Filter F(s) fVCO PLL Synthesizer Chip
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Figure 2. What Is Fractional-N?
DESIGNING WITH THE SA8025 Reference Signal and Divider
Since the synthesized signal is derived from the reference signal, using a clean crystal with an appropriate level is crucial. The reference signal should be AC coupled and deliver between 300 and 600mVP-P to Pin 8 for the input buffer to convert it into a CMOS compatible level. The maximum crystal frequency the part can handle is determined by both analog and digital supplies because the input buffer and the reference divider are powered by VDDA and VDD, respectively. For a VDD = VDDA = 3V configuration, the maximum crystal frequency allowed is 20MHz. When VDD = 3V and VDDA = 5V, this frequency becomes 30MHz.
VCO
fREF
Phase Detector and Charge Pumps
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Figure 1. PLL Synthesizer For conventional synthesizers, the phase detector comparison frequency must be equal to the channel spacing (frequency resolution) because the main divider (N) can only increment and decrement in integer steps. However, the main divider of the fractional-N synthesizer is capable of generating steps to be a fraction of the comparison frequency. Now the total divider ratio consists of an integer part (N) and a fractional part (NF/Q). The numerator (NF) and the denominator (Q, either 5 or 8) of a fraction are controlled through software programming. Referring to Figure 2, to synthesize channels 1680MHz, 1680.3MHz and 1680.6MHz with channel spacing of 300kHz, the values have to be 5600MHz, 5601MHz and 5602MHz, respectively. The channel spacing of a fractional-N synthesizer is a fraction of the comparison frequency. When using the SA8025, the comparison frequency is increased to either 1.5MHz (mod 5) or 2.4MHz (mod 8), yielding a smaller N value of 1120 (mod 5) or 700 (mod 8) to synthesize 1680MHz.
The main and auxiliary phase detectors (see Figure 3) detect both the phase and frequency difference between the divided-down VCO and reference signals. If the main/aux leads the reference, there will be a pulse coming out of the phase detector which turns on the N-type charge pump and sinks current from the low-pass filter. On the other hand, if the main/aux lags the reference, the P-type charge pump will be activated and more current will be delivered to the low-pass filter. Due to the internal delays of CMOS devices, the phase comparator needs a minimum phase difference, backlash time, to generate an output pulse. This backlash time will introduce a dead-zone around zero phase difference where a small phase error cannot be detected. The way the SA8025 eliminates this problem is by having a minimum on-time of 1/fREF for the P pump (sourcing) and N pump (sinking) when the loop is in lock condition, which is shown in Figure 4. Since the charge pump on-time is determined by the crystal reference frequency (fREF), the higher the frequency, the better will be the close-in noise performance. Typically, there will be 3dB close-in noise improvement for a 50% increase in reference frequency (e.g., from 9.6 to 14.4MHz).
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Philips Semiconductors
Application note
SA8025 Fractional-N synthesizer for 2GHz band applications
AN1891
CLOCK DATA STROBE SERIAL INPUT + PROGRAM LATCHES
V DD
VS S EM FB 2 RFIN RFIN 64/65/68/73 PRESCALER MAIN DIVIDERS PR 2 NM1 12
NM2 NM3 8
FB FMOD NF 3 PRESCALER MODULUS CONTROL RF FRD CN RN
FRACTIONAL ACCUMULATOR
TEST
EM MAIN PHASE DETECTOR 2
8
NORMAL OUTPUT CHARGE PUMP CL
PHP SPEED-UP OUTPUT CHARGE PUMP
SM 2 NR V CCP EM+EA MAIN REFERENCE SELECT
2
12 CK 4 INTEGRAL OUTPUT CHARGE PUMP PHI
REFIN
REFERENCE DIVIDER
÷2
÷2
÷2
SA 2 AUXILIARY REFERENCE SELECT EA PA EA 12 NA AUXILIARY PHASE DETECTOR 2
RA
AUXILIARY OUTPUT CHARGE PUMP
PHA
LOCK AUXIN 1/4 PRESCALER AUXILIARY DIVIDER
V DDA
VS S A
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Figure 3. Block Diagram of the SA8025 Since the phase detector detects phase from 2 to 2, its gain (K) equals the charge pump output current (ICP) divided by 2 with units of A/rad. The charge pump output current, ICP (A), is determined by the external resistor RN and the internal registers CN, CK and CL values. The ICP for normal mode operation (PHP pump only) is: CN @ I R N (EQ. 1) I CP + 32 0.5 V * 0.9 * 150(I RN) (EQ. 2) where RN + D D A I RN Figure 5 shows a graphical representation of Eq. 2. The curves are valid for both main and aux synthesizers. Notice that in normal mode, currents due to the CK and CL values are negligible and only the PHP pump is activated. When the part is in speed-up, both charge pumps are on and the ICP for PHP is: CN @ I R N (EQ. 3) (2 CL ) 1 ) 1) I CP + 32 ICP for PHI is: I CP + CN @ I R N (2 CL ) 1) CK 32
(EQ. 4)
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Philips Semiconductors
Application note
SA8025 Fractional-N synthesizer for 2GHz band applications
AN1891
fREF RESET SIGNAL (L) DIVIDED DOWN REFERENCE (R) DIVIDED DOWN MAIN (X) P PUMP N PUMP OUTPUT CURRENT 1/fREF
Using divide ratios below the minimum divide ratio (N') to synthesize channels is possible, but it requires trial and error. For instance, in the Japan Personal Handy Phone System (PHS), the VCO is running at 1646.7 to 1670.1MHz (248.45MHz first IF). Using a modulus 8 fraction with 300kHz channel spacing, the required N value is between 686 and 695, which is less than the N' of the 4 modulus prescaler. Calculation showed that only N = 695 is not obtainable using the 4 modulus prescaler, but it can be obtained using the 64/65/73 prescaler. The B word must be sent to change the prescaler ratio.
Table 1.
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Prescaler Ratio 64/65 64/65/68
PR Bits 01 10 11 00
N' 4032 1348 933 1096
Total Divide Ratio, N N = (NM1 + 2) × 64 + NM2 × 65 N = (NM1 + 2) × 64 + NM2 × 65 + (NM3 + 1) × 68 N = (NM1 + 2) × 64 + NM2 × 65 + (NM3 + 1) × 68 + (NM4 + 1) × 73 N = (NM1 + 2) × 64 + NM2 × 65 + (NM4 + 1) × 73
Figure 4. Phase Detector Timing Diagram
120
64/65/68/73 64/65/73
100
80
V DDA = 3
Determining the Programming Values for NM1, NM2, NM3 and NM4
For the 2-modulus prescaler (64/65), NM1 and NM2 can be determined by: NM2 + 64 @ FRAC NM1 + INT 64 64
R (k )
60
V DDA = 4 V DDA = 5
N
(EQ. 5)
(EQ. 6)
40
N * NM2 * 2
20
where FRAC (...) and INT (...) takes the fractional integer part of the argument.
5
0 20 35 50 65 80 95 110 125 140 Ir (µA)
For the 3-modulus prescaler, NM1, NM2 and NM3 (NM4 when PR = 00) can be determined by:
SR00914
K1 + INT
Figure 5. RN(RA) vs. IRN(IRA) for Different VDDA From Eq. 3 notice that in speed-up mode, the PHP output current will be at least 3 times higher than the normal mode current even though CL=0. Speed-up mode stays active as long as the STROBE signal is high after an A word is sent. Bypass capacitors (100nF) should be used for RN, RF and RA pins to prevent high frequency noise being coupled into the pins causing modulation of the VCO.
N 64 R 3, K2 + FRAC N64R @ 64 (EQ. 7) (EQ. 8) NM3 + INT K2 R (EQ. 9) NM2 + FRAC K2 @ R R
NM1 + K1 * NM2 * NM3 (EQ. 10)
where R = 4 for 64/65/68 prescaler, R = 9 for 64/65/73 prescaler. For the 4-modulus prescaler (64/65/68/73), we first arbitrarily choose NM4 (smaller values are preferable) and then use the following formulas to calculate NM1, NM2 and NM3: 13 13 (EQ. 11) K1 + INT 4, K2 + FRAC 64 64 64
Main Divider
The total divide ratio, N, is determined by the combination of the main divider ratio (NM1, NM2, NM3, NM4) and the prescaler values. The part is internally controlled to produce division ratios of N or N+1 when a fractional function is used. The minimum divide ratio, N', which guarantees that all the channels above this ratio can be synthesized consecutively (no blind channels) is different for each prescaler ratio. Since the fractional-N synthesizer increases the comparison frequency, lower N values can be used. To accomplish this, the SA8025 uses a 4 modulus (64/65/68/73) prescaler that lowers the minimum divide ratio to 933. When programming a total divide ratio (N) which has no components of NM3 or NM4, simply treat them as "don't cares".
N
N
@
K2 * 9 @ NM4 4 2 * 9 @ NM4 @ 4 NM2 + FRAC K 4
NM3 + INT
(EQ. 12)
(EQ. 13) (EQ. 14)
NM1 + K1 * NM2 * NM3 * NM4
Notice that the formulas shown above will give only one set of NM1, NM2, NM3 and NM4 that generates the desired N value. Generating continuous N below 933 (4 modulus) is still possible if all
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Philips Semiconductors
Application note
SA8025 Fractional-N synthesizer for 2GHz band applications
AN1891
four modulus options are used. It was found that the part can generate N continuously from 702. The program "8025NMIN.EXE", provided with the "UMAWINE.EXE" for controlling the SA8025 demoboard, calculates all the N values that the part can generate. Users should run the program to find out the right NM1, NM2, NM3 and NM4 if N value of less than 702 is needed. This program will give only one possible combination of NM1 to NM4 for each N.
program sa8025 Philips Semiconductors, Sunnyvale, CA Author: Wing S. Djen Date: 5/9/94 Purpose: To find the minimum divide ratio on the SA8025 integer i, n1, n2, n3, n4, mod2, mod3a, mod3b, mod4, + delta1, delta2, delta3, delta4, + temp2, temp3a, temp3b, temp4 + lown, highn write(*,*) `Enter the lowest N value' read(*,*) lown write(*,*) `Enter the highest N value' read(*,*) highn do 10 i=lown, highn do 10 n1=0,10 do 10 n2=0,10 do 10 n3=0,10 do 10 n4=0,10 mod2 = (n1+2)*64 + n2*65 mod3a = (n1+2)*64 + n2*65 + (n3+1)*68 mod3b = (n1+2)*64 + n2*65 + (n4+1)*73 mod4 = (n1+2)*64 + n2*65 + (n3 + 1)*68 + (n4+1)*73 delta1 = i-mod2 delta2 = i-mod3a delta3 = i-mod3b delta4 = i-mod4 if (delta1.eq.0) then if (temp2.eq.mod2) goto 1 write(*,5) mod2, n1, n2 5 format(` PR="01" N=',i5,3x,`NM1',i2,3x, + `NM2=',i2) temp2=mod2 endif 1 if (delta2.eq.0) then if (temp3a.eq.mod3a) goto 2 write(*,6) mod3a, n1, n2, n3 6 format(` PR="10" N=',i5,3x,`NM1',i2,3x, + `NM2=',i2,3x,`NM3=',i2) temp3a=mod3a endif 2 if (delta3.eq.0) then if (temp3b.eq.mod3b) goto 3 write(*,7) mod3b, n1, n2, n4 7 format(` PR="00" N=',i5,3x,`NM1',i2,3x, + `NM2=',i2,3x,`NM4=',i2) temp3b=mod3b endif 3 if (delta4.eq.0) then if (temp4.eq.mod4) goto 10 write(*,8) mod4, n1, n2, n3, n4 8 format(` PR="11" N=',i5,3x,`NM1',i2,3x, + `NM2=',i2,3x,`NM3=',i2,3x,`NM4=',i2) temp4=mod4 endif 10 continue end
PR="01" PR="01" PR="01" : : PR="11" PR="00" PR="00" PR="11" PR="11" PR="11" PR="11" PR="11" PR="11" PR="00" PR="11" PR="00" PR="11" PR="00" PR="00" PR="11" PR="11" PR="11" PR="11" PR="11" PR="11" PR="11" PR="00" PR="00" PR="00" PR="11" PR="11" PR="11" PR="11"
N=128 N=192 N=193 : : N=679 N=679 N=680 N=680 N=681 N=682 N=683 N=684 N=685 N=685 N=686 N=686 N=687 N=687 N=688 N=688 N=689 N=690 N=691 N=692 N=693 N=694 N=694 N=695 N=696 N=697 N=698 N=699 N=702
NM1=0 NM1=1 NM1=0 : : NM1=0 NM1=1 NM1=0 NM1=1 NM1=0 NM1=0 NM1=0 NM1=0 NM1=1 NM1=3 NM1=0 NM1=2 NM1=0 NM1=1 NM1=0 NM1=1 NM1=0 NM1=1 NM1=0 NM1=0 NM1=1 NM1=0 NM1=2 NM1=1 NM1=0 NM1=0 NM1=1 NM1=0 NM1=0
NM2=0 NM2=0 NM2=1 : : NM2=1 NM2=3 NM2=4 NM2=1 NM2=2 NM2=0 NM2=3 NM2=1 NM2=1 NM2=0 NM2=2 NM2=1 NM2=0 NM2=2 NM2=3 NM2=0 NM2=1 NM2=1 NM2=2 NM2=0 NM2=0 NM2=1 NM2=0 NM2=1 NM2=2 NM2=0 NM2=0 NM2=1 NM2=0
NM3=4 NM4=3 NM4=3 NM3=2 NM3=2 NM3=5 NM3=0 NM3=3 NM3=1 NM4=4 NM3=1 NM4=4 NM3=4 NM4=4 NM4=4 NM3=2 NM3=2 NM3=0 NM3=0 NM3=3 NM3=1 NM3=1 NM4=5 NM4=5 NM4=5 NM3=2 NM3=0 NM3=0 NM3=1
NM4=1
NM4=2 NM4=2 NM4=1 NM4=3 NM4=2 NM4=3 NM4=3 NM4=2
NM4=3 NM4=3 NM4=4 NM4=4 NM4=3 NM4=4 NM4=4
NM4=4 NM4=5 NM4=5 NM4=5 SR00916
RF Inputs
The RF inputs were designed to be used differentially for better noise rejection. However, the part can also be driven single-endedly with RFIN+ or RFIN pin terminated by a 1nF capacitor. The matching network between VCO and RF input was intended for matching both the VCO and the Main Out on the demoboard to 50 (see Figure 6).
52 18 18 RFIN 51 SA8025 52 52 18
50
VCO
50
SR00917
Figure 6. Matching Network for the RFIN Pin
Lock Detect
The LOCK pin is selectable by software to be either the lock detect indicator, output of the main divider, output of the reference divider, or output of the auxiliary divider. Programming details can be found in the data sheet. The pin voltage will go to VDD once the lock condition has been satisfied. Upon power up, the part is in an unknown state and the LOCK pin may go high. It will be functional only after the part is programmed.
SR00915
The following is a sample output of the "8025NMIN.EXE" program. It shows the divide ratios that cover the PHS band.
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AN-1 AN-2 AN-3 AN-4 AN-5 AN-6 AN-7 AN-8
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