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Part: AN430
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Philips Semiconductors Microcontroller Products
Application note
Using the 8XC751/752 in multimaster I2C applications
AN430
INTRODUCTION
The Philips Semiconductors 83C751/87C751 offers the advantages of the 80C51 architecture in a small package and at a low cost. It combines the benefits of a high performance microcontroller with on-board hardware supporting the Inter Integrated Circuit (I2C) bus interface. The Inter IC (I2C) bus developed by Philips allows integrated circuits to communicate directly with each other via a simple bidirectional 2-wire bus. The comprehensive family of CMOS and bipolar ICs incorporating the on-chip I2C interface offers many advantages to designers of digital control for industrial, consumer and telecommunications equipment. Interfacing the devices in an I2C based system is very simple as they connect directly to the two bus lines: a serial data line (SDA) and a serial clock line (SCL). System design can rapidly progress from block diagram to final schematics, as there is no need to design bus interfaces. In addition, functional blocks on the block diagram correspond to actual ICs. A prototype system or a final product version can be easily modified or upgraded by `clipping' or `unclipping' ICs to or from the bus. The simplicity of designing with the I2C bus does not reduce its effectiveness: it is a reliable, multimaster bus with integrated addressing and data-transfer protocols. The I2C-bus compatible ICs give cost reduction benefits through smaller IC packages and a minimization of PCB traces and glue logic.
The availability of microcontrollers, like the 83C751, with on-board I2C interface is a very powerful tool for system designers. The integrated protocols allow systems to be completely software defined. Software development time of different products can be reduced by assembling a library of re-usable software modules. In addition, the multimaster capability allows rapid testing and alignment of end-products via external connections to an assembly-line computer. The mask programmable 83C751 and its EPROM version, 87C751, can operate as a master or a slave device on the I2C small area network. In addition to the efficient interface to the dedicated function ICs in the I2C family the on-board interface facilitates I/O and RAM expansion, access to EEPROM, and processor-to-processor communications. The 83C752 and its EPROM version, 87C752, are essentially the 83C751/87C751 with the addition of a five channel multiplexed 8-bit A/D converter and an 8-bit PWM output. As the I2C bus interface is identical, the programming example and the discussion relates to both processors. The multimaster capability of the I2C bus allows easy integration and expansion of relatively complex systems, in which different devices can independently initiate data transfers. Integration of a multimaster system is easy as a Master on the bus does not have to coordinate its data transfer with other potential Master devices--arbitration and synchronization are taken care of by the
hardware and bus protocols. Expanding a system with a new device is trivial--it is "clipped" onto the two serial bus lines, and the new device may act as a Master without any modification to the other devices (see Figure 1). Microcontrollers like the S8XC751/752 on the I2C bus are extremely powerful, as they can be programmed to be both Masters and Slaves in the same system. This way the microcontroller may initiate communication on the bus, and when requested, will respond to a data transfer request by another device. In this Application Note we shall discuss the most important technical features of the I2C bus and describe the special I2C hardware interface of the 8XC751/752. We shall demonstrate with an example how the microcontroller can be programmed for a multimaster environment. The communications routines of the example are quite general, and can be ported to many applications--so we shall discuss in detail the software interface to these routines. The description of the 8XC751 I2C interface hardware and part of the general discussion of the I2C bus is similar to Application Note AN422 which dealt with the microcontroller in a single-master environment. Most of the added discussions relate to the multimaster aspects of the bus. Additional information for the I2C bus and the 83C751/752 Microcontroller can be found in the Philips Semiconductors Microcontroller Data Handbook (IC20).
MICROCONTROLLER A
LCD DRIVER
STATIC RAM OR EEPROM
SDA
SCL
GATE ARRAY
ADC
MICROCONTROLLER B
Figure 1. Example of an I2C-bus Configuration
June 26, 1992
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Revision date: June 1993
Philips Semiconductors Microcontroller Products
Application note
Using the 8XC751/752 in multimaster I2C applications
AN430
·
Pull-up Resistors (Serial Data Line) SDA (Serial Clock Line) SCL RP
·
RP
+VD
D
· ·
SCLK
· · ·
SCLK
·
·
SCLK1 Out DATA1 Out
·
SCLK2 Out
·
DATA2 Out
·
SCLK In
DATA In
SCLK In
DATA In
Figure 2. Connection of I2C-bus Devices to the I2C-bus
THE I2C BUS
The two lines of the I2C bus are a serial data line (SDA) and a serial clock line (SCL). A typical system configuration is shown in Figure 2. Each device is recognized by a unique address--whether it is a microcomputer, LCD driver, memory or keyboard interface--and can operate as either a transmitter or a receiver, depending on the function of the device. A device generating a message or data is a transmitter, and a device receiving the message or data is a receiver. Obviously, a passive function like an LCD driver could only be a receiver, while a microcontroller or a memory can both transmit and receive data. Every device connected to the bus must have an open-drain or an open-collector output for both the data (SDA) and the clock (SCL) lines. Each one of the lines is connected to the positive supply via a common pull-up resistor (see Figure 2). This implements a wired-AND function, and each of the bus lines which will have the HIGH level only if all the output transistors tied to it are switched off. Data on the I2C bus can be transferred at a rate up to 100kbit/s. The number of devices connected to the bus is limited only by the maximum bus capacitance of 400pF. As different technology devices can be connected to the I2C bus, the levels of the logical 0 (Low) and logical 1 (High) are not fixed and depend on the appropriate level of VDD.
MASTERS AND SLAVES
When a data transfer takes place on the bus, a device can be either a master or a slave. The device which initiates the transfer, and generates the clock signals for this transfer is the master. At that time any device addressed is considered a slave. It is important to note that a master could be either a transmitter or a receiver: a master microcontroller may send data to a RAM acting as a transmitter, and then interrogate the RAM for its contents acting as a receiver--in both cases being the master initiating the transfer. In the same manner, a slave could be both a receiver and a transmitter. The I2C is a multimaster bus. It is possible to have in one system more than one device capable of initiating transfers and controlling the bus. A microcontroller may act as a master for one transfer, and then be the slave for another transfer, initiated by another processor on the network. The master/slave relationships on the bus are not permanent, and exist per transfer. As more than one master may be connected to the bus it is possible that two devices will try to initiate transfer at the same time. Obviously, in order to eliminate bus collisions and communications chaos, an arbitration procedure is necessary. The I2C design has an inherent arbitration and clock synchronization procedure relying on the wired-AND connection of the devices on the bus. In a typical multimaster system, a
microcontroller program should allow it to gracefully switch between master and slave modes and preserve data integrity upon loss of arbitration.
DATA TRANSFERS
One data bit is transferred during each clock pulse (Figure 3). The data on the SDA line must remain stable during the HIGH period of the clock pulse in order to be valid. Changes in the data line at this time will be interpreted as control signals. A HIGH-to-LOW transition of the data line (SDA) while the clock signal (SCL) is HIGH indicates a Start condition, and a LOW-to-HIGH transition of the SDA while SCL is HIGH defines a Stop condition (Figure 4). The bus is considered to be busy after the Start condition and free again a certain time after the Stop condition. The Start and Stop conditions are always generated by the master. The number of data bytes transferred between the Start and Stop condition from transmitter to receiver is not limited. Each byte, which must be eight bits long, is transferred serially with the most significant bit first, and is followed by an acknowledge bit (Figure 5). The clock pulse related to the acknowledge bit is generated by the master. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, while the transmitting device releases the SDA line (HIGH) during this pulse (Figure 6).
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Philips Semiconductors Microcontroller Products
Application note
Using the 8XC751/752 in multimaster I2C applications
AN430
A slave receiver must generate an acknowledge after the reception of each byte, and a master must generate one after the reception of each byte clocked out of the slave transmitter. If a receiving device cannot receive the data byte immediately, it can force the transmitter into a wait state by holding the clock line (SCL) LOW. When designing a system it is necessary to take into account cases when acknowledge is not received. This happens, for example, when the addressed device is busy in a real time operation. In such a case the master, after an appropriate "time-out", should abort the
transfer by generating a Stop condition, allowing other transfers to take place. These "other transfers" could be initiated by other masters in a multimaster system or by this same master. An exception to the "acknowledge after every byte" rule occurs when a master is a receiver: it must signal an end of data to the transmitter by NOT signalling an acknowledge on the last byte that has been clocked out of the slave. The acknowledge related clock, generated by the master,
should still take place but the SDA line will not be pulled down. In order to indicate that this is an active and intentional lack of acknowledgement, we shall term this special condition as a "Negative ACK". The bus design includes special provisions for interfacing to microprocessors which implement all the I2C communications in software only--it is called "Slow Mode". When all the devices on the network have built-in I2C hardware support the Slow Mode is irrelevant.
SDA
SCL Data Line Stable: Data Valid Change of Data Allowed
Figure 3. Bit Transfer on the I2C Bus
SDA
SDA
SCL S Start Condition P Stop Condition
SCL
Figure 4. Start and Stop Conditions
SDA
MSB
Acknowledgment Signal from Receiver
Acknowledgment Signal from Receiver
Byte Complete, Interrupt within Receiver
Clock Line Held Low While Interrupts Are Serviced
SCL S Start Condition
1
2
7
8
9 ACK
1
2
3-8
9 ACK
P Stop Condition
Figure 5. Data Transfer on the
I2C
Bus
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Philips Semiconductors Microcontroller Products
Application note
Using the 8XC751/752 in multimaster I2C applications
AN430
Data Output by Transmitter MSB Data Output by Receiver
SCL from Master 1 S Start Condition Clock Pulse for Acknowledgment 2 8 9
Figure 6. Acknowledge on the I2C Bus
SDA
SCL
17 S ADDRESS START CONDITION
8 R/W
9 ACK
17 DATA
8
9 ACK
17 DATA
8
9 P ACK STOP CONDITION
Figure 7. A Complete Data Transfer on the I2C-Bus
DATA TRANSFERRED (n BYTES + ACKNOWLEDGE) MASTER WRITE: S SLAVE ADDRESS W A DATA A DATA A P
DATA TRANSFERRED (n BYTES + ACKNOWLEDGE) MASTER READ: S SLAVE ADDRESS R A DATA A DATA NA P (n BYTES + ACKNOWLEDGE)
(n BYTES + ACKNOWLEDGE) COMBINED FORMATS: S S= P= W= R= R/W = A= NA = SLAVE ADDRESS START STOP WRITE READ READ OR WRITE ACKNOWLEDGE NEGATIVE ACKNOWLEDGE R/W A DATA A S SLAVE ADDRESS DIRECTION OF TRANSFER MAY CHANGE AT THIS POINT R/W A
DATA
A
P
Figure 8. I2C Data Formats
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Philips Semiconductors Microcontroller Products
Application note
Using the 8XC751/752 in multimaster I2C applications
AN430
ADDRESSING AND TRANSFER FORMATS
Each device on the bus has its own unique address. Before any data is transmitted on the bus, the master transmits on the bus the address of the slave of this transaction. A well-behaved slave, if it exists on the network, should of course acknowledge the master's addressing. The addressing is done with the first byte transmitted by the master after the Start condition. An address on the network is seven bits long, appearing as the most significant bits of the address byte. The last bit is a direction (R/W) bit. A zero indicates that the master is transmitting (WRITE) and a one indicates that the master requests data (READ). A complete data transfer, comprised of an address byte indicating a WRITE and two data bytes is shown in Figure 7. When an address is sent, each device in the system compares the first seven bits after the Start with its own address. If there is a match, the device will consider itself addressed by the master and will send an acknowledge. The device could also determine if in this transaction it is assigned the role of a slave receiver or slave transmitter, depending on the R/W bit. Each node of the I2C network has a unique seven bit address. The address of a microcontroller is, of course, fully programmable, while peripheral devices usually have fixed and programmable address portions. In addition to the "standard" addressing discussed here, the I2C bus protocol allows for "general call" addressing and interfacing to CBUS devices. When the master is communicating with one device only, data transfers follow the format of Figure 8 where the R/W bit could indicate either direction. After completing the transfer
and issuing a Stop condition, if a master would like to address some other device on the network, it could start another transaction by issuing a new Start. Another way for a master to communicate with several different devices would be by using a "repeated start". After the last byte of the transaction was transferred, including its acknowledge (or Negative ACK), the master issues again a Start, followed by address byte and data, without effecting a Stop. The master may communicate with a number of different devices, combining READS and WRITES. Only after the transfer with the last slave took place, the master issues a Stop and releases the bus. Possible data formats are demonstrated in Figure 8. Note that the repeated start allows for both change of a slave and a change of direction, without releasing the bus. We shall see later on that the change of direction feature can come in handy even when dealing with a single device. In a single master system the repeated start mechanism is more efficient than terminating each transfer with a Stop and starting again. In a multimaster environment the determination of which format is more efficient could be more complicated, as when a master is using repeated starts it occupies the bus for a long time and prevents other devices from initiating transfers.
of memory locations starting at a specific internal address. A typical I2C memory device like the PCF8570 RAM contains a built-in word address register that is incremented automatically after each read or written data byte. When a master communicates with the PCF8570 it must send a sub-address in the byte following the slave address byte. This sub-address is the internal address of the word the master wants to access for a single byte transfer or the beginning of a sequence of locations for a multi-byte transfer. A sub-address is an eight bit byte, unlike the device address it does not contain a direction (R/W) bit, and like any byte transferred on the bus it must be followed by an acknowledge. A memory write cycle is shown in Figure 9(a). The Start is followed by a slave byte with the direction bit set to WRITE, a sub-address byte, a number of data bytes and a Stop signal. The sub-address is loaded into the word address memory. The data bytes which follow will be written one after the other starting with the sub-address location and the register is incremented automatically. The memory read cycle (Figure 9(b)) commences in a similar manner with the master sending a slave address with the direction bit set to WRITE with a following sub-address. Then, in order to reverse the direction of the transfer, the master issues a repeated Start followed again by the memory device address, but this time with the direction bit set to READ. The data bytes starting at the internal sub-address will be clocked out of the device with each followed by a master-generated acknowledge. The last byte of the read cycle will be followed by a Negative ACK, signalling the end of transfer. The cycle is terminated by a Stop signal.
USE OF SUB-ADDRESSES
For some ICs on the I2C bus the device address alone is not sufficient for effective communications and a mechanism for addressing the internals of the device is necessary. A typical example is addressing memories, when we want to access a specific word inside the device or a sequence
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Others parts begin by an
AN-1 AN-2 AN-3 AN-4 AN-5 AN-6 AN-7 AN-8
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