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Part: AN436
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Philips Semiconductors Microcontroller Products
Application Note
"Opti-Mizer" power management for notebook computers using the 8XC752 microcontroller
AN436
INTRODUCTION
With conventional microprocessor based systems, the market was primarily concerned with performance, cost and features. With the advent of hand-held and portable computers, the prominent market requirements focus on size, weight and battery life. Given a mature 386SX/AT architecture that provides more than adequate performance for average notebook application usage, the design challenges for these machines revolve around developing low power systems that maximize battery usage. The features of a notebook PC are usually characterized as weight and battery life. The heaviest component of a PC is usually the battery and the choice of battery is dictated by the power required. Thus the performance of the power management scheme has a direct bearing on both these parameters. The battery life targets for notebook machines is around 5 hours (the air commute time from coast to coast USA).
resources dictate. The external circuitry monitors battery power, system activities and timed events. Conventionally, the external circuitry is comprised of a digital power management ASIC and associated components. The use of this part increases the chip count of the PC system. The power management system has to determine how the system resources are being used. The resource usage of a PC can be determined by monitoring events or activities. User activity is usually determined by monitoring the keyboard controller for keystroke events. Keystroke events can be indicated by interrupts to the PC core logic or IO reads to the keyboard controller location. The power management ASIC solutions on the market today, such as the VADEM/INTEL 82C347, VLSI VL82C312 and INTEL 80C386SL all require external analog support circuitry to completely implement the power management functions. For example, low battery detect is implemented by the use of external comparator chains and complex, close tolerance level detect circuitry. The cost of this external circuitry is usually a significant proportion of the overall cost of the power management solution. The 83/87C752 employs an internal analog-to-digital converter (ADC). The ADC can be used to implement the battery level detection function at no extra cost and with no extra support circuitry. The 83/87C752 is a member of the Philips 8051 family of high performance 8-bit microcontrollers. These processors have been optimized for sequential real time control applications. The 83/87C752 contains most of the features of the 80C51 and has the following features: 2k bytes ROM 64 bytes RAM Single level interrupt structure 16 bit programmable counter/timer Two 8-bit and one 5-bit bi-directional IO ports I2C serial interface PWM with interrupt and overflow capability 5 channels of 8-bit A/D 28-pin DIP and PLCC.
exactly what the designer requires. With the current competitive arena for laptop development, time-to-market and value added features have a significant impact on the sales success of a particular product. The 83/87C752 offers flexibility at a low price. the power management design requirements can be coded and configured in the controller software and One Time Programmable (OTP) devices can offer a quick low-cost implementation of the coded scheme. With these integrated functions that the 83/87C752 offers, and its ability to provide a complete solution to power resource control, this device is emerging to be the industry standard for power management.
TOPOLOGY
Figure 1 shows a block diagram of a typical system implementation. It employs the integrated power management scheme using the Philips microcontroller to handle the keyboard and power management functions. The CPU and coprocessor reside on the local bus with the system memory. A local bus controller monitors CPU bus cycles to see if they are memory or ISA cycles. It also integrates the interrupt and DMA functions. The ISA bus controller processes non-system memory bus cycles. A frequency generator is used to provide the system clocks and clock multiplexing. The peripheral controller integrates the communications and mass storage sub-system. The VGA sub-system shares the ISA bus with the peripheral controller. The VGA controller has associated VGA memory. Figure 2 shows the microcontroller with the external support devices. The frequency generator provides the system clocks. It must have the ability to change the frequency of the clocks without violating the minimum high or low times for the core logic. The Philips microcontroller can control the speed of the system clocks via frequency select pins on the frequency generator. Frequency generators such as the Avasem AV9127 can change the processor clock speed gradually and continuously without violating the minimum high or low times. The integrated controller monitors system activity via its digital input ports. It uses internal timers to time the intervals between activity. The power to the VGA and peripheral sub-systems is controlled by the digital output port pins via MOSFETs. Battery level and VCC is monitored by the onboard A/D converter.
OVERVIEW
Most of the power consumed by a fully powered PC is wasted. The hard disk spins constantly even though data transfers from the disk are very sporadic. PCs may sit unattended for periods where the user is distracted by a telephone call, for instance. There are two principle challenges in designing a power management system: the ability to power down various devices without affecting other devices on the same bus, and ensuring full compatibility with existing operating systems and applications. The largest user of power in a PC is the display sub-system (35 Watts) followed by the peripherals such as the hard disk (24 Watts), the main system memory (0.51.5 Watts), and the core logic (1 Watt).
INTEGRATED POWER MANAGEMENT
The conventional PC architecture needs to be extended to support power management. Hardware needs to be added to provide power-down capabilities and software needs to be added to support the hardware and provide DOS compatibility. The software support is usually realized in the BIOS. The hardware support can be implemented with external circuitry. This external circuitry manages the power resources to individual sub-sections of the PC system as these
FLEXIBILITY
ASIC solutions to power management offer rigid schemes which work adequately with a few notebook architectures, but rarely offer
June 1991
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Revision date: June 1993
Philips Semiconductors Microcontroller Products
Application Note
"Opti-Mizer" power management for notebook computers using the 8XC752 microcontroller
AN436
COREPWR
POWER
POWER SUPPLY
FETS
ISAPWR
CPU
MATH COPROCESSOR
VGAPWR
LOCAL BUS
KEYBOARD
POWER MANAGEMENT UNIT
FREQ GEN
LOCAL BUS CONTROLLER
MEM
SYSTEM MEMORY
REFRESH
K B D A T A
ISA BUS CONTROLLER
ISA BUS
PERIPHERAL COMBO
VGA SUB-SYSTEM
Figure 1. Integrated Power Management Scheme
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FETS ADC ADC PON COREON HDDON FDCON COM1ON COM2ON BACKLIGHTON VGAON CLK2 FREQ GEN BUSCLK CPUS2 CPUS1 CPUS0 83/87C752 FCLS1 FCLS0 SUSPEND *SWSUSPEND *VWE *PWROFF INT0 INT1 KBDATA DBCLK REFSEL TO THE PERIPHERAL CONTROLLER *REFRESH *RAS0 *RAS1 *RAS2 *RAS3 TO THE SYSTEM DRAM
+5V
NiCAD
COM1 RING INDICATOR
Philips Semiconductors Microcontroller Products
COM2 RING INDICATOR
"Opti-Mizer" power management for notebook computers using the 8XC752 microcontroller
Figure 2. External Support Devices
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HIGH INTEGRATION
LOW EXTERNAL PART COUNT
Application Note
AN436
Philips Semiconductors Microcontroller Products
Application Note
"Opti-Mizer" power management for notebook computers using the 8XC752 microcontroller
AN436
OPERATION
The power management system operates like a state machine. Transitions from state to state are controlled by expiring timers which are retriggered by external events. On entering a state, external power is switched or clocks are modified. A typical power management system would employ six states: Full Power, Doze, Shutdown, Sleep, Suspend, and Off. The state diagram of Figure 3 shows the power management states and their interrelationships.
Shutdown
This state is also entered from the FULL POWER state and operates in parallel with the DOZE state. Entry into this state is controlled by an expired timer (typically 30 secs). The timer expired as a result of not being reloaded by a transition on an activity monitor pin. In this state the power to a particular peripheral or group of peripherals is removed via an external FET.
Sleep
This state is entered from either the DOZE state or SHUTDOWN state. Entry into this state is controlled by an expired timer (typically 30 secs). The length of this timer is usually longer than that employed in the DOZE or SHUTDOWN states. The timer expired as a result of not being reloaded by a transition on an activity monitor pin. The activity monitor may look for keystrokes or video activity as described below. In this state power is removed from the backlight and LCD modulation voltage regulator via external FETs.
Shutdown-Doze
This is an intermediate state which implements the features of both the SHUTDOWN and DOZE states. Entry into this state from the DOZE state is controlled by an expired timer (typically 30 secs). The timer expired as a result of not being reloaded by a transition on an activity monitor pin. Entry into this state from the SHUTDOWN state is controlled by an expired timer also. The timer expired as a result of not being reloaded by a transition on an activity monitor input pin. In this state the power to a particular peripheral or group of peripherals is removed via an external FET and the frequency generator is instructed to reduce the clock speed to about half that of the FULL POWER state.
Full Power
Entry to this state is controlled by a transition of the ON/OFF switch. In this state all the power control outputs are asserted, and the clock generator is selected for the highest speed. The system runs at full speed and power.
Suspend
This state is entered from any of the above states. Entry into this state is controlled by a transition on an external suspend switch or a command from the BIOS. During this state, the microcontroller takes over the task of refreshing the system memory and removes the power from the rest of the system via external FETs.
Doze
This state is entered from the FULL POWER state. Entry into this state is controlled by an expired timer (typically 30 secs). The timer expired as a result of not being reloaded by a transition on an activity monitor input pin. In this state the frequency generator is instructed to reduce the clock speed to about half that of the previous state.
Off
This state is entered from any of the above states. Entry into this state is controlled by a transition on an external switch or a command from the BIOS.
LOW KBD ACTIVITY 30 SECS.
FULL POWER
RESUME SWITCH LOW PERIPHERAL ACTIVITY BIOS
DOZE
ACTIVITY
SHUTDOWN
SWITCH SUSPEND
LOW PERIPHERAL ACTIVITY
SHUTDOWN DOZE
LOW KBD ACTIVITY 30 SECS.
LOW KBD ACTIVITY 3 MINS.
LOW KBD ACTIVITY 3 MINS.
SUSPEND TIMER
SLEEP
OFF POWER STATE FLOW DIAGRAM BIOS COMMAND POWER SWITCH
Figure 3. Multi-State Power Management Scheme
June 1991
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Philips Semiconductors Microcontroller Products
Application Note
"Opti-Mizer" power management for notebook computers using the 8XC752 microcontroller
AN436
POWER MANAGEMENT ELEMENTS
Figure 4 shows the internal power management elements of the Philips controller. The Activity monitors contain combinatorial algorithms to monitor or poll an activity or combination of activities. The activity monitors reload programmable timers which toggle clock control and power control output pins. Each functional block is discussed in more detail below.
the state of the MOSFET. This is necessary to handle the default powerup mode of the port pins. For a lower performance and cost reduced system, a logic level FET can be used such as a MTM25N06L and driven directly from the microcontroller port. These logic level FETs usually have Rds on specifications in the region of 100 milliohms. The finite drain-source resistance implies that a small amount of power is wasted in this channel while power is applied to the switched group of devices.
Timers
The timers should run independently of the keyboard scanning function. The timers are used as timeouts for a combination of external events or activities. The timers are constructed of reloadable timers and reloaded by transitions or conditions on external events. A typical timeout period is between 1 and 4 minutes, therefore the timeout must be constructed from both timer hardware and support software. Figure 7 shows the interrelationships between hardware and software. The software must record the instances of timeout cycles. If the number of cycles is allowed to reach a predetermined number, the timeout elapses and the assigned power control output is negated, or the clock control outputs proceed to the next state. The count of the number of cycles is reset by a command for the activity monitor. The activity monitor asserts flags during the background and interrupt tasks. The timer software processes these flags to determine the state of the timeout. The software uses a count variable to measure the instances of the timer elapsing and a flag to determine whether activity has occurred.
Power Outputs
The power outputs are logic level signals that control MOSFETs via level shifting circuitry. The MOSFETs switch power to the various blocks under power management control and are chosen to have a low Rds on which reduces the voltage drop across the DRAIN-SOURCE channel. The level shifting circuitry and MOSFET orientation is shown in Figure 5. C1 and R1 control the switchon edge and should be chosen to make the edge sufficiently slow to minimize the inrush current. This is necessary where the notebook computer employs solid chip tantalum capacitors which fail short-circuit on switchon current transients. R1 pulls the gate to the NiCAD supply rail. The NiCAD battery voltage is usually greater than +12 Volts. We can exploit this relatively high voltage to turn the MOSFETs hard on and further reduce the Rds on. The NPN transistor is operated as a cascode and gives no net inversion between the logic level and
Clock Control
The clock control module controls the speed of the system clocks. Where the notebook system has a synchronous ISA clock, it is derived directly from CLK2, the processor clock. The clock control outputs can be fed directly to a frequency generator such as an AVASEM AV9127 where pins are committed to encode a frequency select scheme. The scheme employs two programmable clock generators; one with eight preset frequencies used for the system clock; and the other with four preset frequencies used for the mass storage subsystem. Figure 6 shows the interconnection between the clock control port and frequency generator. By changing the assignments of the encoded select lines, the system clock frequency can be reduced. Frequency generators employ analog voltage controlled oscillators which, when instructed to change frequency, will steadily and gradually change frequency in a smooth transition. This scheme does not violate the minimum high and low times for the core logic devices.
Activity Monitor
The activity monitor sets the activity flags for the timers. The monitors contain combinatorial elements which poll an external activity or a number of external activities. External activity can be detected by transitions or levels on input port pins. The interrupt pins would be better suited for transition detect while the general input ports could be used to poll for external conditions. There are several key activity indicators on the PC. See Table 1 below.
Table 1. Key Activity Indicators
SIGNAL *IDECS1 *IDESC0 *VWE *FDCS *LPTRDY *GPRD *53C90SEL *LIDSW TYPE LEVEL LEVEL EDGE LEVEL LEVEL EDGE EDGE LEVEL DEVICE/PERIPHERAL Hard Disk IDE interface chip select Hard Disk IDE interface chip select VGA Memory Write enable signal Floppy disk digital control register Parallel printer interface flag Accessory interface select SCSI interface chip select Notebook lid switch
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AN-1 AN-2 AN-3 AN-4 AN-5 AN-6 AN-7 AN-8
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